International Business Machines Corporation

Globalfoundries Inc.

Richard James Eickemeyer

Brian William Thompto

Dung Q Nguyen

Hung Qui Le

Balaram Sinharoy

David S Levitan

John Barry Griswell, Jr

Stamatis Vassiliadis

Sheldon Bernard Levenstein

Nadeem Malik

Mauricio J Serrano

Avijit Saha

Benjamin W Stolt

John Michael Borkenhagen

Andrew Henry Wottreng

Brian David Barrick

Steven R Kunkel

William Thomas Flynn

Ehsan Fatehi

Guy L Guthrie

Bartholomew Blaner

Brian R Konigsburg

Mohit Karve

Tejas S Karkhanis

Harold F Kossman

Charles Gorham Ward

Alper Buyuktosunoglu

Pradip Bose

David Arnold Luick

Bernard Charles Drerup

Robert H Bell, Jr

David Allen Hrusecky

Albert James Van Norstrand, Jr

Ronald Nick Kalla

Elizabeth A McGlone

Venkat Rajeev Indukuru

Steven J Battle

George W Rohrbaugh, Iii

Tu-An T Nguyen

Nicholas R Orzol

Mehul N Patel

Timothy John Mullins

Naga P Gorti

Edmund Joseph Gieske

Jeffrey Powers Bradford

Madhavi Gopal Valluri

Ophir Erez

Pattabi Michael Seshadri

Ross Evan Johnson

Douglas Robert Logan

Alan Vicha Pita

Douglas R G Logan

Michael K Gschwind

Jeffrey A Stuecheli

Philip George Emma

Michael Stephen Floyd

Ravi Nair

Jose Eduardo Moreira

Sundeep Chadha

Hans Mikael Jacobson

Lixin Zhang

Susan Elizabeth Eisen

Lee Evan Eisen

Bradly George Frey

Wen-Tzer Thomas Chen, Jr

Yaoqing Gao

William Elton Burky

Wael R El-Essawy

Timothy Hume Heil

Francis Patrick O'Connell

Miles Robert Dooley

Richard William Doing

Robert Alan Philhower

Kimberly Marie Fernsler

Thomas L Jeremiah

Jason Nathaniel Dale

John Wesley Ward, Iii

Jeffrey Richard Summers

Zhigang Hu

James Allen Rose

Duane Arlyn Averill

Kevin Curtis Griffin

Mikko Herman Lipasti

James L Denton

Thomas W Chen, Jr

James Ira Brookhouser

Sandra Kay Ryan

William E Speght

Douglas Robert Gordan Logan

A method of performing instructions in a computer processor architecture includes determining that a load instruction is being dispatched. Destination related data of the load instruction is written into a mapper of the architecture. A determination that a compare immediate instruction is being dispatched is made. A determination that a branch conditional instruction is being dispatched is made. The branch conditional instruction is configured to wait until the load instruction produces a result before the branch conditional instruction issues and executes. The branch conditional instruction skips waiting for a finish of the compare immediate instruction.

Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction

A system, processor, programming product and/or method including: an instruction dispatch unit configured to dispatch instructions of a compare immediate-conditional branch instruction sequence; and a compare register having at least one entry to hold information in a plurality of fields. Operations include: writing information from a first instruction of the compare immediate-conditional branch instruction sequence into one or more of the plurality of fields in an entry in the compare register; writing an immediate field and the ITAG of a compare immediate instruction into the entry in the compare register; writing, in response to dispatching a conditional branch instruction, an inferred compare result value into the entry in the compare register; comparing a computed compare result value to the inferred compare result value stored in the entry in the compare register; and not execute the compare immediate instruction or the conditional branch instruction.

Inferring future value for speculative branch resolution in a microprocessor

Methods and systems for determining a priority of a threads is described. A processor can execute branch instructions of the thread. The processor can predict branch instruction outcomes of the branch instructions of the thread. The processor can increment a misprediction count of the thread in response to an actual execution of a branch instruction of the thread being different from a corresponding branch instruction prediction outcome of the thread. The processor can determine the priority of the thread based on the misprediction count of the thread.

Thread priorities using misprediction rate and speculative depth

Aspects of the invention include includes determining a first instruction in a processing pipeline, wherein the first instruction includes a compare instruction, determining a second instruction in the processing pipeline, wherein the second instruction includes a conditional branch instruction relying on the compare instruction, determining a predicted result of the compare instruction, and completing the conditional branch instruction using the predicted result prior to executing the compare instruction.

Inferring future value for speculative branch resolution

A computer processor includes a dispatch stage and a dependency skipping execution unit. The dispatch stage is configured to dispatch a plurality of instructions that include a general purpose instruction configured to produce first data, a dependent instruction configured to produce second data, and an indirect dependent instruction configured to produce third data. The dependency skipping execution unit is configured to monitor the plurality of instructions and to process the indirect dependent instruction in response to the general purpose instruction producing the first data. The indirect dependent instruction is issued independently from the second data produced by the indirect dependent instruction.

Dependency skipping execution

Processing data in an information handling system is disclosed that includes: in response to an event that triggers a flushing operation, calculate a finish ratio, wherein the finish ratio is a number of finished operations to a number of at least one of the group consisting of in-flight instructions, instructions pending in a processor pipeline, instructions issued to an issue queue, and instructions being processed in a processor execution unit; compare the calculated finish ratio to a threshold; and if the finish ratio is greater than the threshold, then do not perform the flushing operation. Also disclosed is moving the flush point.

Flushing of instructions based upon a finish ratio and/or moving a flush point in a processor

According to one or more embodiments, an example computer-implemented method for executing one or more out-of-order instructions by a processing unit, includes decoding an instruction to be executed, and based on a determination that the instruction is a store instruction, identifying a split load-hit-store (LHS) table for the store instruction, wherein a LHS table of the processing unit includes multiple split LHS tables. Identifying the split LHS table includes determining, for the store instruction, a first split LHS table by performing a mod operation using one or more operands from the store instruction, and adding one or more parameters of the store instruction in the first split LHS table by generating an ITAG for the store instruction. The method further includes dispatching the store instruction for execution to an issue queue with the ITAG.

Splitting load hit store table for out-of-order processor

Techniques are disclosed for identifying data streams in a processor that are likely to benefit from data prefetching. A prefetcher receives at least a first request in a plurality of requests to pre-fetch data from a stream in a plurality of streams. The prefetcher assigns a confidence level to the the first request based on an amount of confirmations observed in the stream. The request is in a confident state if the confidence level exceeds a specified value. The first request is in a non-confident state if the confidence level does not exceed the specified value. Doing so allows a memory controller to determine whether to drop the at least the first request based on the confidence level and a memory resource utilization threshold.

Prefetch confidence and phase prediction for improving prefetch performance in bandwidth constrained scenarios

Predicting indirect branch instructions may comprise predicting a target address for a fetched branch instruction. Accuracy of the target address may be tracked. The fetched branch instruction may be flagged as a problematic branch instruction based on the tracking. A pattern cache may be trained for predicting a more accurate target address for the fetched branch instruction, and the next time the fetched branch instruction is again fetched, a target address may be predicted from the pattern cache.

Predicting indirect branches using problem branch filtering and pattern cache

Instruction prefetching in a computer processor includes, upon a miss in an instruction cache for an instruction cache line: retrieving, for the instruction cache line, a prefetch prediction vector, the prefetch prediction vector representing one or more cache lines of a set of contiguous instruction cache lines following the instruction cache line to prefetch from backing memory; and prefetching, from backing memory into the instruction cache, the instruction cache lines indicated by the prefetch prediction vector.

Instruction prefetching in a computer processor using a prefetch prediction vector

Aspects of the invention include a computer-implemented method for executing one or more instructions by a processing unit. The method includes fetching, by an instruction fetch unit, a first instruction from an instruction cache. The method further includes associating, by an effective address table logic, an entry in an effective address table (EAT) with the first instruction. The method further includes fetching, by the instruction fetch unit, a second instruction from the instruction cache, wherein the first instruction occurs before a branch has been taken and the second instruction occurs after the branch has been taken. The method further includes associating at least a portion of the entry in the EAT associated with the first instruction in response to the second instruction utilizing a cache line utilized by the first instruction and processing the first instruction and the second instruction through a processor pipeline utilizing the entry of the EAT.

Effective address table with multiple taken branch handling for out-of-order processors

A technique for operating a processor includes allocating an entry in a prefetch filter queue (PFQ) for a cache line address (CLA) in response to the CLA missing in an instruction cache. In response to the CLA subsequently hitting in the instruction cache, an associated prefetch value for the entry in the PFQ is updated. In response to the entry being aged-out of the PFQ, an entry in a backing array for the CLA and the associated prefetch value is allocated. In response to subsequently determining that prefetching is required for the CLA, the backing array is accessed to determine the associated prefetch value for the CLA. A cache line at the CLA and a number of sequential cache lines specified by the associated prefetch value in the backing array are then prefetched into the instruction cache.

Dynamic sequential instruction prefetching

A technique for operating a processor includes identifying a difficult branch instruction (branch) whose target address (target) has been mispredicted multiple times. Information about the branch (which includes a current target and a next target) is learned and stored in a data structure. In response to the branch executing subsequent to the storing, whether a branch target of the branch corresponds to the current target in the data structure is determined. In response to the branch target of the branch corresponding to the current target of the branch in the data structure, the next target of the branch that is associated with the current target of the branch in the data structure is determined. In response to detecting that a next instance of the branch has been fetched, the next target of the branch is utilized as the predicted target for execution of the next instance of the branch.

Techniques for predicting a target address of an indirect branch instruction

A processor core supporting out-of-order execution (OOE) includes load-hit-store (LHS) hazard prediction at the instruction execution phase, reducing load instruction rejections and queue flushes at the dispatch phase. The instruction dispatch unit (IDU) detects likely LHS hazards by generating entries for pending stores in a LHS detection table. The entries in the table contain an address field (generally the immediate field) of the store instruction and the register number of the store. The IDU compares the address field and register number for each load with entries in the table to determine if a likely LHS hazard exists and if an LHS hazard is detected, the load is dispatched to the issue queue of the load-store unit (LSU) with a tag corresponding to the matching store instruction, causing the LSU to dispatch the load only after the corresponding store has been dispatched for execution.

Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions

Growing community of inventors

Rochester, MN, United States of America

Richard James Eickemeyer