Ati Technologies Inc.

Broadcom Corporation

Ati International Srl

Richard J Selvaggi

Larry Alan Pearlstein

Gary W Root

Richard Sita

Michael G Frank

Gary J Lavelle

Stephen C Dilliplane

Jack Tseng

James G Maino

A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value.

SIMD processor with register addressing, buffer stall and methods

A SIMD processor responds to a single min/max instruction to find the minimum or maximum valued data unit in an array of data units. The determined minimum/maximum value and an associated index value thereto may be output. Alternatively, the value of a data unit in another array may be output at a corresponding location. A further single instruction executable by the SIMD processor, may be applied to results obtained using such a single min/max instruction, to allow such instructions to operate on two dimensional arrays.

SIMD processor executing min/max instructions

A method for processing video image data including a plurality of different image data types begins by providing tasks to be performed on each different image data type. The image data is divided into a plurality of groups based on the image data type. A set of arithmetic operations required to accomplish the tasks provided for the corresponding image data type is determined. Each arithmetic operation is assigned to one of a plurality of commonly used arithmetic units which performs the arithmetic operation, whereby each image data type is transformed in accordance with the corresponding provided tasks. The transformed image data of each group is combined, completing the processing.

Vertex data processing with multiple threads of execution

An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Methods and apparatus for processing variable length coded data

In a multiprocessor system, a task control processor may be placed in the path connecting each execution processor to a system bus. Such task control processors may detect the completion of a first task on an associated execution processor and, responsively, generate commands to lead to the initiation of a second task on the same, or another, execution processor. Such task completion detection and task initiation by the task control processors removes, from a central processor or the execution processors, the burden of performing such tasks, thereby improving the efficiency of the entire system.

Method and apparatus for managing tasks in a multiprocessor system

A SIMD processor includes an ALU having data interconnects facilitating the concurrent processing of overlapping data portions of at least one operand store. Such interconnects facilitate the calculation of shift-invariant convolutions, and sum of absolute differences between an operand in the operand store and another operand.

SIMD processor having enhanced operand storage interconnects

The result of eight find_min_16 of lookup-min_16, find_max_l6x, lookup_max_16 instructions may be stored in memory storage units of operand storage, using SIMD at addressing techniques detailed in U.S. patent application Ser. No. 10/929,992, filed Aug. 30, 2004 and entitled SIMD PROCESSOR AND ADDRESSING METHOD.

A video processor integrates the processing of video and graphics data by restructuring the discrete blocks of luminance and chrominance component data associated with video image data (Y,U,V) into composite pixel values (YUYV), and performing the subsequent processing, in particular motion compensation, upon this composite data form. The discrete blocks of video image data are queue and processed in parallel to form a composite pixel value associated with each pixel within the image areas represented by the discrete blocks. By forming composite pixel values for reference data and error term data, common processing elements can be optimized and used for both video and graphics image processing. For example, the trilinear interpolator commonly used for 3-D graphics filtering and texturing can be used to form predicted macroblocks for motion compensation, and the specular adder used for graphics lighting effects can be used to process the motion compensation error terms.

Video processor with composite graphics and video picture elements

Multi-thread video data processing for use in a computer video display system. The parameters of vertex data are grouped into a plurality of groups. The computation needs of each group are broken down into several arithmetic operations to be performed by corresponding arithmetic units. The units concurrently process the vertex data.

An apparatus and method allows efficient processing of vertex data received in any suitable format. The method and apparatus accesses stored vertex data that may be stored in a plurality of different formats. A single copy of the received vertex data is stored in memory so that the system does not require a block of memory containing differing formats of the vertex data. The apparatus and method utilizes a universal vertex data fetching mechanism which controls retrieval of vertex data stored in the first format in memory based on multi-format description data. As such, the vertex data that may be received in one of a plurality of formats, is effectively coded so that a data fetcher may appropriately fetch vertex parameter data from suitable addresses independent of the format in which the vertex data was received.

Multi-format vertex data processing apparatus and method

A memory access device is presented that synchronously transfers data between contiguous memory locations and a set of potentially non-contiguous registers, via a single load, or move, command. An address generator generates a series of contiguous memory addresses and a corresponding set of potentially non-contiguous register addresses in dependence upon the contents of a variable format command. In this manner, the data transfer efficiencies achievable by a block transfer of contiguous data elements can be achieved while simultaneously transferring the data to and from non-contiguous register locations. The memory access device may also include a data converter which optionally converts the data elements contained in memory to and from another form, such as from integer to floating point, during the data transfer process.

Variable format memory access device

A graphics processing device includes a variable performance setup engine that processes vertexes of polygons to create surface coefficients, and a rasterizer that processes the surface coefficients to create pixel values corresponding to each pixel location within each polygon. The variable performance setup engine is structured so as to provide the surface attributes of each polygon within a time that is correlated to the size of the polygon. In this manner, the overall polygon processing rate will be substantially related to the size of the polygon. By providing a short processing time for small polygons, and a longer processing time for larger polygons, the image processing rate is shown to be less dependent upon the sizes of the polygons that comprise the image. The invention thereby provides for an overall image processing rate that is substantially independent of the complexity of the image being rendered.

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Doylestown, PA, United States of America

Richard J Selvaggi