Prolinx Labs Corporation

Other

Jigsaw Tek, Inc.

Richard J Nathan

Steve S Chiang

James J Lan

William H Shepherd

Robert Osann, Jr

A carrier for an integrated chip is embedded into a substrate, so that stresses due to thermal expansion are uniformly distributed over an interface between the substrate and the carrier (hereinafter 'embedded carrier'). Such an embedded carrier may be formed of a material having a coefficient of thermal expansion similar or identical to the coefficient of thermal expansion of an integrated circuit chip to be mounted thereon, so as to eliminate stresses (due to thermal expansion) at joints between the carrier and the integrated circuit chip. The just-described joints may be formed by any method well known in the art, e.g. flip-chip bonding. Such packaging of one or more integrated circuit chip(s) eliminates reliability issues associated with conventional flip chip bonded components, which are caused by, for example, concentration of stresses in conventional solder ball interconnections between a chip and a substrate.

Embedded carrier for an integrated circuit chip

One or more integrated circuit chips each containing conductive pads on one surface, are embedded in a substrate such that the conductive pads are exposed and the one surface of each chip is substantially coplanar with a top surface of the substrate. Electrically conductive material is placed over the one surface, including conductive pads, of each chip and the top surface of the substrate and patterned, using standard semiconductor or printed circuit photolithographic and processing techniques to form an electrically conductive interconnect pattern connecting the one or more integrated circuit chips into an electronic system. When a single integrated circuit chip is to be embedded in a substrate, the invention makes possible the simultaneous manufacture of a plurality of such packaged integrated circuit chips in a single large substrate using standard semiconductor or printed circuit photolithographic and processing techniques and then singulating the large substrate into a plurality of smaller substrates, each containing a single integrated circuit chip. Likewise, when more than one integrated circuit chip is embedded in a substrate, a plurality of such structures can be manufactured in a single large substrate and then singulated into a plurality of smaller substrates, each containing more than one integrated circuit chips.

Integrated package and methods for making same

Two types of programmable elements, fuses and antifuses, are disclosed for interconnecting the terminals of electronic components mounted on printed circuit boards (PCBs), multichip modules (MCMs) or in integrated circuit packages (IC packages). Both types of programmable elements can be fabricated as part of the regular processes used to fabricate PCBs, MCMs, or IC package (pin grid array). For fuses and antifuses, the material, geometry and dimensions can be varied to minimize the real estate and maximize programming efficiency (reduce programming time). Each type of programmable element, fuse or antifuse, can be separately used in matrices to form programmable board and package substrates. When both types of programmable elements are used together, more efficient placement and route architectures take advantage of the characteristics of each type of programmable element. Furthermore, combinations of both fuses and antifuses in the same structure allows the architecture to be reprogrammable. Fuse and antifuses can be easily used to form programmable burn-in boards and field programmable smart cards, credit cards, sockets and cable connectors.

Programmable/reprogrammable printed circuit board using fuse and/or

Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable cable in one embodiment and a cable adapter in another embodiment. The cable and the cable adapter can be used for interconnecting a cable connector of a first configuration to a cable connector of a second configuration.

Programmable cable and cable adapter using fuses and antifuses

Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable burn-in board in one embodiment and an electrically programmable device-under-test (DUT) card in another embodiment. Both types of programmable elements can also be used in a reconfiguration device for interconnecting electrical contacts in a first configuration to electrical contacts in a second configuration. The various embodiments of this invention include, for example, a component socket, a socket adapter, a cable, a cable adapter, a scrambler card for a burn-in board and a device-under-test card for a burn-in board. A method for forming a fuse is also disclosed.

Programmable/reprogramable structure using fuses and antifuses

A device-under-test card includes a matrix of fuses and/or antifuses formed as part of a multi-layered structure. The matrix of fuses and/or antifuses can be electrically programmed to connect any one of first electrical contacts to any one of second electrical contacts and so allows the device-under-test card to act as a junction between burn-in board traces couplable to signal drivers and/or receivers and burn-in board traces couplable to terminals of a device-under-test. The device-under-test card also includes a discrete resistor or alternatively a resistor ladder that permits a terminal of a device-under-test to be coupled to a power or ground terminal or to any combination of resistances including a short, in addition or as an alternative to any one of various signal drivers and/or receivers.

Device-under-test card for a burn-in board

Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable socket adapter in one embodiment. The socket adapter can be used for interconnecting an electronic component having terminals in a first configuration to electrical contacts in printed circuit board.

Apparatus including a programmable socket adapter for coupling an

A programming method in accordance with this invention partitions traces of a fuse matrix into groups wherein each group contains traces connected to fuses that are to remain intact. All of the traces in a group are connected to a first voltage so that the fuses between traces in the group are subjected to minimal currents. In one embodiment, all of the traces that are not in the group connected to the first voltage are connected to a second voltage such that a programming current passes through fuses to be programmed. In an alternative embodiment, traces in a second group are connected to the second voltage and all of the remaining traces are shorted to each other.

Growing community of inventors

Morgan Hill, CA, United States of America

Richard J Nathan