Elsag International B.v.

Elsag International N.v.

Richard J Molnar

Joseph C Nemer

Edward Bastijanic

David J Wroblewski

Shanthala Narayanaswamy

Michael J Wozniak

A system for loading upgraded, that is, new boot code and/or main firm ware has a programmable memory that has two boot code regions. One of the regions holds the active boot code while the other region holds the inactive boot code. During a boot code upgrade, the boot code in the inactive region, is under control of the boot code in the active region, replaced with the new boot code. Once the replacement process is verified as having been successful and the vector table in the new boot code is copied to the processor vector table in the memory, the processor can be reset so that the new boot code becomes the active boot code and the previously active boot code becomes the inactive boot code.

Method and apparatus for upgrading firmware boot and main codes in a programmable memory

A digital implementation for a carrier detector. The detector determines if the carrier frequency at any instant is within a predetermined frequency band. The detector further determines if the detected frequency remains within the predetermined frequency band for a predetermined period of time. The detector also provides an indication that there has not been any loss of carrier for another predetermined period of time.

Method and apparatus for performing carrier detection

Digital supervisory and diagnostic circuitry to provide a watchdog function and a low voltage detect function and diagnostics for those functions. The watchdog function has a high immunity to EMI and RFI disturbances and may be enabled or disabled as necessary. An indication is provided of the cause of the last reset so that a reset due to EMI can be distinguished from a reset due to a power failure. The low voltage detect circuitry is implementable in an integrated circuit chip. The low voltage detect circuitry eliminates oscillations from the reset signal and provides a delay which is programmable by the user. The circuitry is designed so that the length of the delay can never be zero.

Method and apparatus for performing supervisory functions in digital

A sigma-delta technique is used to generate a digital representation of the incoming analog signal amplitude. The integration stage of the converter holds an analog error term relative to the ratio of an incoming analog input signal to a reference voltage. The incoming analog signal is disconnected at the end of the conversion. The error term is monitored through a comparator as charge packets are applied to the input of the integration stage. The number of charge packets needed to have the error term cross zero provides information which can be used to extend the resolution of the analog to digital converter.

Method and apparatus for extending the resolution of a sigma-delta type

A process and apparatus for shadowing memory uses a single memory chip which is addressable into an address field which is smaller than the memory chip. A program having a main control portion is programmed into a main memory area of the memory chip and is directly connected to a main address space of the address field. The program also includes a plurality of secondary program portions which can be used one at a time with the main control portion of the program. Each of the secondary program portions is stored in a separate secondary and shadowed memory area of the memory chip. A secondary address space of the address field which is large enough to accommodate only one secondary memory area at a time, is controlled so as to be latched to only one secondary memory area at a time. Latching is achieved through higher bits of address locations in a selected portion of the address field. Interrupt and power-up routines are provided in the main portion of the program to avoid entering and leaving the program through different secondary program portions.

Process controller single memory chip shadowing technique

A device which is a combination of a method and apparatus and a filter, such as but not limited to, a conventional lag filter for digitally processing and filtering signals used in industrial control applications. The method and apparatus provides a factor which is used by the filter to process the digital signal at the input to the device. The method determines if the change in the input signal is either due to noise or a valid signal change. Information which gives a past analysis of the trend in direction of the signal at the input to the device is used in the method. The trend information includes a factor representative of the past history of the trend. The method uses the most recent trend indicator to determine to a reasonable degree of confidence if the signal currently at the input to the device is or is not characteristic of noise. If the signal at the input is not believed to be characteristic of noise, then the method adjusts the trend indicator by a tracking credit. The tracking credit is, in effect, a further degree of confidence that change in the input signal is not characteristic of noise. The method minimizes the tradeoff between valid signal response time and noise rejection associated with the prior art filters.

Method and apparatus for digitally processing and filtering signals in

The characteristics of the field process system controlled by a self tuning controller are obtained by analyzing the open loop response of the process variable to a step applied at the controller's control output. A first-order system response with pure time delay is used to approximate a higher-order field process system's actual response. The overall deadtime and time constant of the first-order approximation are determined. The maximum slope of the process variable response to the step is stored along with an assigned time of its occurrence and an assigned process variable. The stored information is used to approximate the overall deadtime. In one embodiment the stored information is assumed to be the data obtained from a second-order response having a 10:1 time constant ratio and is used to find the assumed second-order time constants which are used to find the first-order time constant. In a second embodiment the first order time constant is determined by using a convergence point falling within a predetermined range between the actual response data and the first-order approximation. The step is not applied to the control output until the process variable has reached the initial steady state condition and the calculation of slope ceases when the process variable response reaches the final steady state condition. Alternative techniques are disclosed for determining the steady state condition.

Method and apparatus for obtaining process characteristics in a

Process command controller

An input circuit for conditioning a control signal having a variety of waveforms and voltage levels, comprises a pair of input terminals having a metal oxide varistor connected thereacross. One terminal is connected to the base of a transistor thru a resistor, the emitter of the transistor driving an opto-coupler for isolating the control signal from a micro-processor which receives the control signal over an inverter having a schmitt trigger input.

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Willoughby, OH, United States of America

Richard J Molnar