Intel Corporation

Micron Technology Incorporated

Richard J Harries

Pramod Malatkar

Terry Lee Sterrett

Sudarashan V Rangaraj

Robert L Sankman

Mitul Bharat Modi

Bob Sankman

Shankar Ganapathysubramanian

Sankara J Subramanian

Sudarshan V Rangaraj

Yonggang Li

Dilan Seneviratne

Sandeep B Sane

Praneeth Kumar Akkinepally

Kyle Yazzie

Vassoudevane Lebonheur

Ameya Limaye

Naga Sivakumar Yagnamurthy

Vassou Lebonheur

Xuefei Wan

An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.

Electronic package that includes lamination layer

Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.

Apparatuses and methods to enhance passivation and ILD reliability

The present description relates to the field of fabricating microelectronic packages, wherein a microelectronic device may be attached to a microelectronic substrate with a compensator to control package warpage. The warpage compensator may be a low coefficient of thermal expansion material, including but not limited to silicon or a ceramic material, which is positioned on a land-side of the microelectronic device to counteract the thermal expansion effects of the microelectronic device.

Thermal expansion compensators for controlling microelectronic package warpage

Methods and designs for increasing interconnect areas for interconnect bumps are disclosed. An interconnect bump may be formed on a substrate such that the interconnect bump extends beyond a contact pad onto a substrate. An interconnect bump may be formed on a larger contact pad, the bump having a large diameter.

Interconnection designs and materials having improved strength and fatigue life

Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface. Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the electrical connections.

Using collapse limiter structures between elements to reduce solder bump bridging

A linear coefficient of thermal expansion (CTE) mismatch between two materials, such as between a microelectronic die and a mounting substrate, may induce stress at the interface of the materials. The temperature changes present during the process of attaching a die to a mounting substrate can cause cracking and failure in the electrical connections used to connect the die and mounting substrate. A material with a CTE approximately matching the die CTE is introduced in the mounting substrate to reduce the stress and cracking at the electrical connections between the die and mounting substrate. Additionally, this material may comprise thin film capacitors useful for decoupling power supplies.

Embedded capacitors for reducing package cracking

A compliant structure for an electronic device comprises a substrate () composed of a first material () and a compliant zone () within the substrate. A plurality of solder joints () are located between, and form a connection between, the substrate and the electronic device (). The compliant zone reduces the degree of deformation experienced by the solder joints due to thermal mismatch loading between the substrate and the die during attachment of the die to the substrate (chip attach). This reduction in solder joint deformation reduces the likelihood that the solder joints will crack.

Compliant structure for an electronic device, method of manufacturing same, and system containing same

A molding compound cap structure is disclosed. A process of forming the molding compound cap structure is also disclosed. A microelectronic package is also disclosed that uses the molding compound cap structure. A method of assembling a microelectronic package is also disclosed. A computing system is also disclosed that includes the molding compound cap structure. The molding compound cap includes a configuration that exposes a portion of a microelectronic device.

Growing community of inventors

Chandler, AZ, United States of America

Richard J Harries