Intel Corporation

Richard J Greco

Jonathan M Eastep

Federico Ardanaz

Robert Valentine

Gilbert A Neiger

Mark Jay Charney

Jesus Corbal

Rajesh M Sankaran

Edward Thomas Grochowski

Eriko Nurvitadhi

Koichi Yamada

Thomas D Fletcher

Joseph Nuzman

Deborah T Marr

Stephen R Van Doren

Paul Caprioli

Lokpraveen B Mosur

Dennis Ryan Bradford

Narayan Ranganathan

Kent D Glossop

Niall D McDonnell

Jonathan D Pearce

Ganesh Venkatesh

Jeffrey J Cook

Asit K Mishra

Dwight P Manley

David B Sheffield

Tracy Garrett Drysdale

David N Lombard

Nicholas P Carter

Michael A O'Hanlon

Ilya Sharapov

Milind Baburao Girkar

Avinash Sodani

Alan Beecher Kyker

Andreas Kleen

Ramkumar Nagappan

Christopher M Cantalupo

Robert J Kyanko

Rohit Banerjee

Hari K Nagpal

Steve S Sylvester

Krishnakanth Venkata Sistla

Paul S Diefenbaugh

Andrew J Herdrich

Eugene Gorbatov

John H Crawford

Ian M Steiner

Anil K Kumar

Suresh S Chittor

Wayne D Smith

Micah Barany

David W Archer

Rob F Van Der Wijngaart

Jim Sutton

Stephanie Labasan

Don Breazeal

Dominick D DeLillo

Niall D Mcdonnell

Michael A O'HANLON

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Systems, methods, and apparatuses for heterogeneous computing

Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.

Holistic global performance and power management

Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.

Systems and methods for synergistic software-hardware power budget management

In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.

Providing multiple memory modes for a processor including internal memory

Methods and apparatus to provide a hybrid power management approach are described. Some embodiments redefine the interface to Power Control Unit (PCU) allowing a hybrid implementation where software running on CPU (Central Processing Unit, also referred to herein interchangeably as 'processor') cores performs more of the work for power management, enabling the PCU to remain as a simple or regular microcontroller. Other embodiments are also disclosed and claimed.

Hybrid power management approach

Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.

Systems and methods for dynamic spatial power steering

Systems and methods may provide a set of networked computational resources such as nodes that may be arranged in a hierarchy. A hierarchy of performance balancers receives performance samples from the computational resources beneath them and uses the performance samples to conduct a statistical analysis of variations in their performance. In one embodiment, the performance balancers steer power from faster resources to slower resources in order to enhance their performance, including in parallel processing.

Dynamic hierarchical performance balancing of computational resources

Systems, apparatuses and methods may provide for obtaining, by a system level reallocator in a plurality of reallocators arranged in a hierarchical tree, resource budget information. Additionally, application performance information may be obtained by at least one of the plurality of reallocators. Moreover, a performance imbalance between a plurality of compute subtrees associate with the application performance information may be reduced by the at least one of the plurality of reallocators and based at least in part on the resource budget information and the application performance information.

Mitigating load imbalances through hierarchical performance balancing

Growing community of inventors

Hillsboro, OR, United States of America

Richard J Greco