Intel Corporation

Richard J Glass

Madhu S Athreya

Keith A Drescher

Debendra Das Sharma

Sanjay Dabral

Theodore Zale Schoenborn

Tessil Thomas

Andrew W Martwick

David G Ellis

Mark B Trobough

Bharadwaj Pudipeddi

Larry R Tate

Jay Joseph Nejedlo

Piyush N Desai

Keshavram N Murty

David Sams

Robert Roth

Mike Wiznerowicz

Colin Looi

A method is described that comprises receiving a timing exposure packet having timestamp information. The timestamp information identifies a cycle of a clock signal at which the packet was made available for transfer from a core to a physical layer within a component of a link-based computing system. The packet having been transmitted from the physical layer and also having phase information. The phase information identifies a cycle of the clock signal at which the packet was transferred from the core to the physical layer.

Correlation technique for determining relative times of arrival/departure of core input/output packets within a multiple link-based computing system

In one embodiment, a state machine may enable retraining of a link, where the state machine is to be initiated responsive to an external input received from a logic analyzer coupled to the link or a periodic timer. Such external input may indicate that the logic analyzer has lost synchronization with respect to link communications, and the retraining thus enables the logic analyzer to regain resynchronization. Other embodiments are described and claimed.

Enabling resynchronization of a logic analyzer

In one embodiment, the present invention includes a method for receiving an error correction code for information from a first port of a first agent and receiving the information from a second port of the first agent by probing a first link under test that couples the first agent and a second agent. The code may be used to validate the information, e.g., in a probe receiver during test or debug operations. Other embodiments are described and claimed.

Providing error correction coding for probed data

A method is described that involves within a link based computing system, opportunistically transmitting, into a network utilized by components of the link based computing system, one or more packets that contain computing system state information. The computing system state information includes software state information created through execution of software by said link based computing system. The method also involves collecting the computing system state information at a monitoring and/or debugging system attached to the link based computing system in order to analyze the link based computing system's operation.

Opportunistic transmission of computing system state information within a link based computing system

A transaction detection device is described having inputs to couple to communication lines. Each communication line to transport notification of a packet observed by a link probe within a computing system containing point-to-point links between nodes. Each of said nodes having at least one processing core. The transaction detection device also comprises logic circuitry to determine from said notifications whether a looked for transaction has occurred within said computing system.

Transaction detection in link based computing system

A scheme for exposing internal debug values in an in-band means via debug packets that are injected sequentially with normal link traffic on a link and do not interrupt or otherwise interfere with normal operation of the link or related devices. Therefore, this proposal does not require additional pins since the debug values are exposed via debug packets in an in-band means along with normal link traffic and the debug values are exposed synchronously with normal link traffic since the debug packets are injected sequentially.

Method, apparatus and system for facilitating debug for link interconnects

According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.

High performance serial bus testing methodology

An assembly including a processor socket having a cut region. The assemble further including a probe board having a repeater positioned in alignment with the cut region. The repeater is to receive at least a first signal. The repeater is to tap the first signal. The tapped first signal is to be transmitted to a first device. The repeater is also to reinject the first signal, and the reinjected first signal to be transmitted to a processor.

Method and apparatus to probe bus signals using repeaters

Debug information is delivered over a general purpose interface. The debug information is delivered in packet format. These packets are referred to as Debug Event Packets (DEP). The debug event packets include a number of debug event bits that if set denote the occurrence of run-time programmable (selectable) debug events. The debug information packet also may include a debug parameter byte that allows one device to pass extra debug information to another device. The debug parameter byte may be associated with one of the debug event bits. The transfer of the debug event packets occurs in-band.

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Olympia, WA, United States of America

Richard J Glass