Bae Systems Information and Electronic Systems Integration Inc.

Richard J Ferguson

Daniel L Stanley

Joseph R Marshall, Jr

Dale A Rickard

Jason F Ross

David D Moser

Richard Brosh

Jeffrey Alan Zimmerman

Alan F Dennis

Lloyd Brown

William C Singleton

Landon J Caley

George A Sawyer

John T Matta

Marla J Lassa

Dean Saridakis

Techniques are provided for a radiation hardened memory system. A memory system implementing the techniques according to an embodiment includes a redundancy comparator configured to detect differences between data stored redundantly in a first memory, a second memory, and a third memory. The redundancy comparator is further configured to identify a memory error based on the detected differences. The memory system also includes an error collection buffer configured to store a memory address associated with the memory error, and a memory scrubber circuit configured to overwrite, at the memory address associated with the memory error, erroneous data with corrected data. The corrected data is based on a majority vote among the three memories. The memory system further includes a priority arbitrator configured to arbitrate between the memory scrubber overwriting and functional memory accesses associated with software execution performed by a processor configured to utilize the memory system.

Triple modular redundancy (TMR) radiation hardened memory system

Techniques are provided for non-volatile detection of an overvoltage condition in a circuit of interest. A circuit implementing the techniques according to an embodiment includes a fuse configured to provide a non-volatile indication of an overvoltage event, the indication associated with an open state of the fuse. The circuit also includes a voltage controlled current switch coupled in series to the fuse. The voltage controlled current switch is configured to enable current flow through the fuse in response to a supply voltage exceeding a threshold value associated with the overvoltage event. The current causes the fuse to switch from a closed state to an open state providing a non-volatile record of the overvoltage event. In some embodiments, the voltage controlled current switch can be a Zener diode with a breakdown voltage based on the threshold value, or a transistor configured to switch into conducting mode at the threshold value.

Non-volatile overvoltage detector

A method for modifying a portion of a substrate after production is described herein. The method can include diagnosing a circuit operation error causing a malfunction, identifying a first contact on the substrate, and connecting, electrically, the first contact to a second contact with at least one trace. The trace is done with a focused ion beam. The method can include diagnosing an error on an operative area of a post-manufacture circuit board causing a malfunction; introducing a metal precursor into a focused ion beam chamber; ionizing the metal precursor by contacting it with a gallium ion beam into a conductive metal and a further ion; depositing a first portion of a conductive metal onto a substrate to form a first trace; and forming the first trace between the operative area and a non-operative area thereby connecting the operative area and the non-operative area.

Post-production substrate modification with FIB deposition

The system and method of using a debug interface recorder and replay unit for debugging and testing devices of interest such as integrated circuits by using a debug interface buffer controller to receive, record, and replay sequences of instructions to the integrated circuit. This is particularly useful for deployed devices that are difficult or dangerous to access. This is also beneficial for devices that cannot be reached (e.g., after launch). By recording sequences and storing them for later use, and by communicating commands and configuration settings to a device, system maintenance and troubleshooting is accomplished saving valuable time and money without requiring physical access to the device of interest.

Debug interface recorder and replay unit

An MCM-HIC device flexibly adds enhanced features to a VLSI 'core' IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one 'chiplet' that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or 'mixed' chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.

Multi-chip hybrid system-in-package for providing interoperability and other enhanced features to high complexity integrated circuits

A method for providing a power estimation for an electronic system is disclosed. Initially, a system architecture of an electronic system design is initially developed, and the system architecture of the electronic system design is then converted to a power flow architecture of the electronic system design. For each power domain within the power flow architecture of the electronic system design, a power domain type is designated. Subsequently, power information are added to the power flow architecture of the electronic system. Finally, a power roll-up calculation is performed on the power flow architecture of the electronic system design in order to yield a final system power value for the electronic system design.

Method and apparatus for providing power estimations for electronic system designs

A system and method for an automated way of running spice on a small portion of a design is presented. The system includes a sub-circuit netlist generation processor and an analog simulation processor. The sub-circuit netlist generation processor generates a sub-circuit netlist based, at least in part, on a HDL netlist, a parasitic capacitance database and trace rules. The sub-circuit netlist contains significantly fewer paths than the HDL netlist of an entire design so that its simulation time is much quicker. The analog simulation processor generates analog simulation results of the sub-circuit netlist based, at least in part, on dynamic inputs.

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Bealeton, VA, United States of America

Richard J Ferguson