Intel Corporation

Richard J Durante

Mickey L Fandrich

Rodney R Rozman

Geoffrey A Gould

Timothy Wade Goodell

Jerry A Kreifels

Keith F Underwood

Owen W Jungroth

Mamun Ur Rashid

Robert E Larsen

Ranjeet Alexis

Alan E Baker

Thomas C Price

Salim B Fedel

Alexander C Mitchell, Iii

Scott M Doyle

A flash memory that could not have completed an operation within a time required by a host may be able to work with the host by dividing the operation into phases that may be completed within the allocated time. As a result, a type of memory that would otherwise be unable to be implemented in a format, such as a memory card, may be used effectively.

Dividing a flash memory operation into phases

A method and apparatus for synchronizing a micro controller in a flash memory device. An interface circuit receives a user command over a host bus. A synchronizer circuit enables an oscillator circuit if the user command specifies an operation on a flash cell array. The oscillator circuit generates a clock signal for synchronizing the micro controller. After completion of the program or erase operation, the synchronizer circuit disables the oscillator circuit if a subsequent user command that specifies another program or erase operation for the micro controller is not pending.

Synchronizing user commands to a microcontroller in a memory device

A method of queuing erase commands for a nonvolatile memory utilizes placeholder commands to prevent the depth of an operation queue from limiting the number of block erase commands that can be queued at one time. The method includes the step of storing a first erase command in the operation queue. The first erase command is designated as a placeholder erase command if no placeholder command is stored in the operation queue. Each of the first and placeholder erase commands designates at least one block of the nonvolatile memory to be erased. Each block has a corresponding status indicator. If a placeholder erase command is already stored in the operation queue, then 1) the corresponding status indicator for the block designated by the first erase command is set to indicate that the first erase command is an absorbed erase command, and 2) the first erase command is removed from the operation queue. If a program command designating the same block as any of the placeholder and absorbed erase commands is stored in the operation queue, then 1) an erase operation for the same block is performed; 2) the corresponding status indicator for the same block is cleared; and 3) the program command is executed. If the program command does not designate the same block as any of the placeholder and absorbed erase commands, then 1) the program command is executed; and 2) the program command is removed from the operation queue.

Methods for queuing and absorbing erase commands in a nonvolatile memory

The pipeline architecture minimizes delays incurred during execution of branch instructions. While a first instruction is executing, a second instruction is fetched and is ready for execution at the beginning of the next clock cycle. Control logic examines the fetched instruction during the first clock cycle to determine whether the instruction is a branch instruction which may indicate that the address of the next instruction is not the next sequential address. Flags which indicate the state of the system are examined to determine if the address of the instruction is the next sequential address or the address indicated in the branch instruction. As this is performed during the fetch clock cycle of the branch instruction, during execution of the branch instruction, the instruction at the address selected is fetched and is ready for execution without delay.

Circuitry and method for performing branching without pipeline delay

A method of prioritizing program and erase commands received in an operation queue for a memory includes the step of storing a placeholder erase command in the operation queue. Subsequent erase commands are absorbed by 1) storing the subsequent erase command in the operation queue; 2) setting a corresponding status indicator for the block designated by the subsequent erase command; and 3) removing the subsequent erase command from the operation queue, wherein the subsequent erase command becomes an absorbed erase command. If a program command that designates a same block as any one of the placeholder and absorbed erase commands is stored in the operation queue, then 1) the same block is erased; 2) the status indicator for the same block is cleared, if the same block is associated with the absorbed command; 3) the program command is executed; and 4) the program command is removed from the operation queue. If the program command does not designate a same block as any one of the placeholder and absorbed erase commands, then 1) the program command is executed; and 2) the program command is removed from the operation queue. In either case, the method then returns to continue absorbing subsequently received erase commands. This allows more erase commands to be queued for execution than what the depth of the operation queue otherwise permits.

Methods for prioritizing erase and program commands in a nonvolatile

A method of prioritizing program commands relative to erase commands in an operation queue for a memory includes the step of initiating an erase of a first block for a first erase command in the operation queue. The memory has a status indicator for each block. The status indicator indicates whether an erase command for its corresponding block has been received and removed from the operation queue but not yet executed (e.g., an absorbed erase command). An interrupt window is executed during the erasure of the first block to determine if the operation queue has received a second command for a second block. If the second command is a program command, then one of three steps is executed. If the first and second blocks are the same, then execution of the program command is deferred until after the erasure of the first block is complete. If the first and second blocks are not the same then the program command is either executed or deferred in accordance with the status indicator for the second block. If the status indicator for the second block indicates that it has been absorbed (e.g., it is set), then execution of the program command will be deferred until after the erasure of the first block is complete. Otherwise, if the status indicator for the second block indicates that it has not been absorbed (e.g. not set), then the erasure of the first block will be interrupted to execute the program command.

Method of prioritizing subsequently received program and erase commands

A flash memory device having a page buffer circuit providing a shared resource between a flash array controller circuit and a user. The page buffer circuit comprises a Plane A and a Plane B, wherein each of the planes A and B is a static random access memory array. The page buffer circuit further comprises a mode control circuit for enabling access to the planes A and B over a host bus in a user mode and access to the planes A and B by the flash array controller in a flash array controller mode.

System and method for allocating and sharingpage buffers for a flash

A nonvolatile memory includes a memory array and a buffer circuit for applying data read from the memory array to external circuitry. A compensation circuit is coupled to the buffer circuit for providing output compensation to the buffer circuit when enabled. The buffer circuit has (1) a first output speed when the compensation circuit is enabled and (2) a second output speed when the compensation circuit is disabled. A configuration circuit is coupled to the compensation circuit for selectively enabling the compensation circuit such that the buffer circuit can be configured between the first and second output speeds. A method of configuring a nonvolatile memory between a first output speed and a second output speed is also described.

Nonvolatile memory with output mode configuration

A flash memory device including programmable code store circuitry. The code store circuitry stores algorithms used by an array controller to erase and program a nonvolatile main memory array. The code store circuitry includes a nonvolatile instruction memory, which stores instructions. The code store circuitry also includes a number of support circuits, such as address decode circuitry, sense path circuitry, main array interface circuitry and several voltage generators. These circuits operate in several modes. In read mode, these support circuits ensure that the instruction data stored in the instruction memory is output to the array controller. In program and erase modes, the support circuits allow control of voltage level applied to the instruction memory and output of instruction to data to the user. In other words, these modes permit modification of the instruction memory. The support circuits are placed in the various modes via control signals output from control registers. Because these control registers are accessible to the device user, the user controls the mode in which the code store circuitry operates.

Method and apparatus for programming an array controller in a flash

A memory device includes a cell array having a plurality of memory cells and a read/write circuit having circuitry for selecting, writing, and reading the memory cells according to a plurality of control signals. A control register circuit is provided that has at least one control register coupled to communicate over a central control bus. A control access circuit is provided that receives an access request targeted for the control register, and translates the access request into an access cycle on the central control bus. The access cycle loads the control register and causes the control register circuit to generate the control signals. The control access circuit receives the access request targeted for the control register from an array controller circuit that generates the access request to load the control register and generate the control signals according to a user command received over a host bus. The control register includes an address decode circuit, a function decode circuit, a master data latch, a slave data latch, and a read control circuit.

Memory device with a central control bus and a control access register

A flash memory device having a flash cell array comprising a plurality of flash cells, a flash array controller circuit for performing program and erase operations on the flash cell array according to a queue operation, and an interface circuit for generating the queue operation according to a user command and a set of command parameters received over a host bus. The interface circuit determines a set of limited resource control bits for the user command and queues the user command and associated parameters to the flash array controller circuit.

Flexible user interface circuit in a memory device

A method and device for selectively enabling and disabling write access to flash blocks in a flash memory device. A lock command locks and unlocks a flash block in a flash array containing a plurality of flash blocks. A block data row decoder selects a block data area of the flash block, and a block status row decoder selects a block status area of the flash block. A lock bit in the block status area is programmed to a first logic state if the lock command specifies a lock flash block operation, or to a second logic state if the lock command specifies a release flash block operation. If a write protect input, read from the write protect pin of the flash memory device, indicates that a write lock is enabled and if a block enabled status bit in a block status register corresponding to the block indicates that the block has the write lock, then the lock bit is read and stored into the block enabled status bit in the block status register corresponding to the block. The write protect input is read again from the write protect pin and if the write protect input indicates that the write lock is enabled, and if the block enabled status bit in the block status register corresponding to the block, as updated, indicates that the block has the write lock, then an error is signaled.

Method and device for selectively locking write access to blocks in a

A method of, and apparatus for, storing and prioritizing among erase block and program word commands is described for a nonvolatile memory device. This prevents the depth of an operation queue responsible for queuing program and erase commands from limiting the number of erase commands that are stored at one time. The first erase command received serves as a place holder, holding a place within the operation queue for all subsequently received erase commands. All subsequently received erase commands are absorbed and cleared from the operation queue. As a result, the operation queue may receive additional commands and an erase command may be queued for every block of memory within the nonvolatile memory device. Absorbed erase commands can be prioritized in response to subsequently received program commands. Blocks are flagged for priority erasure using a priority register. Additionally, interrupt windows located at safe points permit interruption of erase operations to handle command interrupts. The erasure of one or more blocks can be suspended so that a program word command can be serviced thereby permitting program word commands to jump ahead of erase block commands in the queue. Furthermore, a query can be made to determine the status of any block and the block status query will consider pending commands in the operation queue when determining the block status for the block queried.

Method and circuitry for queuing snooping, prioritizing and suspending

A processor which includes at least a pair of call stacks and a pair of register files which may be utilized for running processes. The processor includes circuitry for detecting when an interrupt has occurred and switching from a stack and registers being utilized by a running process to a clean stack and registers to be utilized by the interrupting process. The processor then runs an interrupt start process which places the process interrupted and the circuitry utilized by that process into a condition in which the process may be safely interrupted. Similarly, the process circuitry detects when the interrupt is completed, performs a context switch in which the original stack and register are again made available, and switches to a process adapted to place the interrupted routine in an appropriate state to restart.

Method and apparatus for providing a context switch in response to an

A method of enabling access to a test mode of a semiconductor memory in response to user commands. The method enables test mode access only when a number of 'keys' are presented in the proper sequence via the memory device pins. During the first phase of the unlocking process, an array controller determines whether the correct confirmation codes were input via the address and data pins. If they were, the array controller proceeds to the second phase of the unlocking process. During the second phase voltage levels on selected control pins are checked for a transition to a first voltage level. If the control pins transition as required, the array controller proceeds to the third phase. During the third phase, the array controller waits a limited time for receipt of a second test mode enable command. The second test mode enable command must be followed by correct confirmation codes. If the third phase is successfully completed, the array controller writes to a test mode enable access register. As a result, an enable test mode signal becomes active, which allows the user interlace to respond to subsequently issued test mode commands. Also described is a method of eliminating access to the test mode of the semiconductor memory device, which includes a nonvolatile instruction memory.

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Citrus Heights, CA, United States of America

Richard J Durante