Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Hewlett Packard Enterprise Development LP

Hewlett-packard Development, L.p.

Richard J Carter

J Barry Shackleford

Frederick A Perner

Muhammad Shakeel Qureshi

Ludmila Cherkasova

Alan Hersh Karp

Rajiv Gupta

Gregory Stuart Snider

Wei Yi

Frederic C Amerson

Matti Antero Vanninen

John F Shelton

Motoo Tanaka

Evan Chiu

Mark S Miller

Razvan George Costea

Ross M Wille

Raja Shekar Chelur Siddalingaiah

Frekerick Perner

Example implementations relate to buffer-based update of state data. In example embodiments, a computing device may obtain current state data from a first buffer and determine next state data based at least on the current state data. The computing device may also obtain last difference data that corresponds, for example to current state data that is different from previous state data. The last difference data may be obtained, for example, using a difference data identifier. The computing device may store the last difference data in the second memory buffer. The computing device may also store in the second memory buffer new difference data corresponding to differences between the next state data and the current state data. The computing device may also update the difference data identifier based on the new difference data.

Buffer-based update of state data

A hyperconverged data storage system including a storage array. A first node includes hardware and a virtualization layer supporting guest virtual machines running first applications. An active first virtual storage controller executing in the first virtualization layer is configured for handling IOs accessing the storage array. A second node includes hardware and a second virtualization layer supporting guest virtual machines running second applications. A second virtual storage controller executing in the second virtualization layer operates in a standby mode to the first virtual storage controller. An internal communication network facilitates communications between the first node and the second node. The first virtual storage controller when operating in active mode is configured for handling IOs originating from the first applications and the second applications.

Hyperconverged infrastructure supporting storage and compute capabilities

A method for programmed-state detection in memristor stacks includes applying a first secondary switching voltage across a memristor stack to produce a first programmed-state-dependent secondary switching response in a memristor in the memristor stack. The programmed-state-dependent secondary switching response results in a detectable change in the electrical resistance of the memristor stack. The method also includes measuring a first electrical resistance of the memristor stack and inferring the programmed state of the memristor stack from the measured electrical resistance.

Programmed-state detection in memristor stacks

A method of switching a memristive device in a two-dimensional array senses a leakage current through the two-dimensional array when a voltage of half of a switching voltage is applied to a row line of the memristive device. A leakage compensation current is generated according to the sensed leakage current, and a switching current ramp is also generated. The leakage compensation current and the switching current ramp are combined to form a combined switching current, which is applied to the row line of the memristive device. When a resistance of the memristive device reaches a target value, the combined switching current is removed from the row line.

Method and circuit for switching a memristive device in an array

A programmable current-limited voltage buffer. The programmable current-limited voltage buffer includes at least one current-bias circuit, an inverter, a write-current set control circuit, and an adaptive current limiter. The inverter is coupled to the current-bias circuit and a reference-voltage source, and is configured to couple a row line to either the current-bias circuit, or the reference-voltage source, in response to an input signal. The adaptive current limiter is coupled to the current-bias circuit and to the write-current set control circuit, and is configured to limit current flowing through the memory element in a write operation. An integrated circuit device is also provided, along with a method for current limiting a memory element during switching in an array of memory elements.

Programmable current-limited voltage buffer, integrated-circuit device and method for current-limiting a memory element

Embodiments of the present invention are directed systems and methods for reading the resistance states of crossbar junctions of a crossbar array. In one aspect, a system includes one or more sense amplifiers connected to column wires of the crossbar array, a reference row wire connected to each sense amp, and a wire driver connected to the reference row wire and configured to drive the reference row wire. The sense amplifiers are configured so that when a selected row wire of the crossbar array is driven by a sense voltage, the column wires are held at approximately zero volts and pass currents through the column wires and sense amplifiers to the reference row wire so that resistive voltage losses along the reference row wire substantially mirror the resistive voltage losses along the selected row wire, allowing the sense amplifiers to determine the crossbar junction resistance states.

Systems and methods for row-wire voltage-loss compensation in crossbar arrays

An extensible three dimensional circuit having parallel array channels includes an access layer and crossbar array layers overlying the access layer and being electrically connected to the access layer. The crossbar array layers include parallel channels, the parallel channels being formed from two classes of vias, the first class being pillar vias connected to relatively short stub lines, and the second class being traveling-line vias connected to long lines that travel away from the via; pillar vias and traveling-line vias being configured to connect to crossing lines such that each crossing point between the lines is uniquely addressed by one pillar via and one traveling-line via. Programmable crosspoint devices are disposed between the crossing lines.

Extensible three dimensional circuit having parallel array channels

A storage manager provides data privacy, while preserving the benefits provided by existing hash based storage systems. Each file is assigned a unique identifying code. Hashes of the content-derived chunks of the file are calculated based on the content of the chunk and the code identifying the file. When a request to store a chunk of data is received, it is determined whether a chunk associated with the hash has already been stored. Because hashes are based on privacy-preserving codes as well as content, chunks of duplicate copies of a file need not be stored multiple times, and yet privacy is preserved for content at a file level. In other embodiments, hashes indicating whether a given file is public and/or indicating the identity of the requesting user are also sent with storage requests. These additional hashes enable more robust transmission and storage efficiency, while still preserving privacy.

Protecting the privacy of files referenced by their hash

A method for handling peripheral signals in an extensible three dimensional circuit includes forming an extensible three dimensional circuit with a plurality of stacked crossbar arrays and at least one class of traveling lines which travel vertically and laterally through the circuit. The method also includes alternating the traveling direction of bundles of traveling lines such that there are a substantially equal number of undriven lines and underutilized lines which exit out of a given side of the circuit and creating loopback traces which connect the undriven traveling lines and the underutilized traveling lines to form driven traveling lines with a full complement of memory elements and eliminate addressing gaps within the circuit.

Peripheral signal handling in extensible three dimensional circuits

An extensible three dimensional circuit includes an access layer and crossbar arrays overlying the access layer. The crossbar arrays are formed from tiled mini-arrays of crossing lines and electrically accessed by the access layer. The crossing lines comprise at least one bundle of traveling lines, the at least one bundle of traveling lines moving through the circuit both laterally and vertically. Programmable crosspoint devices are disposed between the crossing lines.

Extensible three dimensional circuit

A seedable pseudo-random number generator. A linear feedback shift register (LFSR) arrangement is used to generate a first pseudo-random number, and a cellular automata is used to generate a second pseudo-random number. The bits of the LFSR arrangement are XORed with bits of the cellular automata to generate the output pseudo-random number.

Seedable pseudo-random number generator

An HTTP server is programmed to detect timed-out client requests by inferring states of its client-server connections. These connections, being full-duplex, can each be viewed as including a client-to-server channel and a server-to-client channel. The state of the server-to-client channel can be inferred by examining local server information to determine whether the client-to-server channel is still established. The server processes a request by a client if the inferred state indicates that the server-to-client channel is still established, and the server terminates the client request if the inferred state indicates that the server-to-client channel is no longer established. Consequently, the server does not expend resources by processing timed-out or dead client requests.

System for aborting response to client request if detecting connection between client server is closed by examining local server information

The present invention is a counter that takes advantage of the speed and implementation of the LFSR counter by utilizing separate digit counters, each digit counter having a period that is a relative prime to the other digit counter periods. The total period will be the product of all the digit counter periods. Since all digits count independently, there is no carry structure between the digits and hence no delay incurred by carry chains. The pseudorandom number counting sequence for each digit still occurs but is ameliorated by the fact that the digital periods are small and can readily be converted to decimal equivalents by table-lookup and residue lookup.

Long-period counter without carries

The present invention provides a method and apparatus to significantly accelerate the searching process based on the Monte Carlo principle and the lattice model. Specifically, the energy status of a lattice-based protein conformation is evaluated by modeling the folding process through a pipelined digital circuit using a number of state machines. The pipelined digital circuit reduces the time required for the determination of the energy status of a particular conformation and, therefore, significantly accelerates the searching speed for the lowest energy status. The present invention also permits real-time tuning of problem parameters by the experimenter.

Growing community of inventors

Los Altos, CA, United States of America

Richard J Carter