Globalfoundries Inc.

Advanced Micro Devices Corporation

Richard J Carter

Hong Yu

Michael John Hargrove

George Jonathan Kluth

Zhenyu Hu

Andy C Wei

Manfred Eller

Srikanth Balaji Samavedam

Qi Zhang

Hongliang Shen

Lun Zhao

Sruthi Muralidharan

Manoj Joshi

Huang Liu

Jin Ping Liu

Rohit Pal

John G Pellerin

Bongki Lee

Hyucksoo Yang

Amy L Child

Kisik Choi

Xusheng Kevin Wu

Xiang Hu

Bingwu Liu

Zhao Lun

Daniel T Pham

Akshey Sehgal

Dae Geun Yang

Dae-han Choi

Mariappan Hariharaputhiran

Seong Yeol Mun

Ying H Tsang

Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).

Integrated circuits with varying gate structures and fabrication methods

Circuit fabrication methods are provided which include, for example: providing one or more gate structures disposed over a substrate structure, the substrate structure including a first region and a second region; forming a plurality of U-shaped cavities extending into the substrate structure in the first region and the second region thereof, where at least one first cavity of the plurality of U-shaped cavities is disposed adjacent in one gate structure in the first region; and expanding the at least one first cavity further into the substrate structure to at least partially undercut the one gate structure, without expanding at least one second cavity of the plurality of U-shaped cavities, where forming the plurality of U-shaped cavities facilitates fabricating the circuit structure. In one embodiment, the circuit structure includes first and second transistors, having different device architectures, the first transistor having a higher mobility characteristic than the second transistor.

Fabrication methods facilitating integration of different device architectures

Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.

Epitaxial block layer for a fin field effect transistor device

In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits

One illustrative method disclosed herein includes, among other things, removing at least one, but not all, of a plurality of first features in a first patterned mask layer so as to define a modified first patterned masking layer, wherein removed first feature(s) correspond to a location where a final isolation structure will be formed, performing an etching process though the modified first patterned masking layer to form an initial isolation trench in the substrate, and performing another etching process through the modified first patterned mask layer to thereby define a plurality of fin-formation trenches in the substrate and to extend a depth of the initial isolation trench so as to define a final isolation trench for the final isolation structure.

Methods of removing fins so as to form isolation structures on products that include FinFET semiconductor devices

In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

Integrated circuit having multiple threshold voltages

The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures.

Uniform exposed raised structures for non-planar semiconductor devices

Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finFETs. Stressor regions are used to increase carrier mobility. However, subsequent processes such as deposition of flowable oxide and annealing can damage the stressor regions, diminishing the amount of stress that is induced. Embodiments of the present invention provide a protective layer of silicon or silicon oxide over the stressor regions prior to the flowable oxide deposition and anneal.

Methods for preventing oxidation damage during FinFET fabrication

Approaches for forming an oxide cap to protect a semiconductor device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming an oxide cap over a subset (e.g., SiP regions) of raised source drain (RSD) structures on the set of fins of the FinFET device to mitigate damage during subsequent processing. The oxide spacer is deposited before the removal of a nitride capping layer from the FinFET device (e.g., by a hot phosphorus wash). The oxide cap on top of the RSD structures will be preserved throughout the removal of the nitride capping layer to provide hardmask protection during this process.

Preventing EPI damage for cap nitride strip scheme in a Fin-shaped field effect transistor (FinFET) device

Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.

Overlay performance for a fin field effect transistor device

Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.

Devices and methods of forming fins at tight fin pitches

Circuit fabrication methods are provided which include, for example: providing the circuit structure with at least one gate structure extending over a first region and a second region of a substrate structure, the at least one gate structure including a capping layer; and modifying an etch property of at least a portion of the capping layer of the at least one gate structure, where the modified etch property inhibits etching of the at least one gate structure during a first etch process facilitating fabrication of at least one first transistor in the first region and inhibits etching of the at least one gate structure during a second etch process facilitating fabrication of at least one second transistor in the second region.

Modified, etch-resistant gate structure(s) facilitating circuit fabrication

A semiconductor device includes a layer of semiconductor material having an active transistor region defined therein, an isolation trench formed in the semiconductor material adjacent the active transistor region, and a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench. The device has an insulating material in the lined trench, and high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, such that the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.

Semiconductor device with isolation trench liner

A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.

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Saratoga Springs, NY, United States of America

Richard J Carter