Intel Corporation

Ncr Corporation

Richard I Mellitz

Ilango S Ganga

Adee Ofir Ran

Kent C Lusted

Roy M Stevens

David L Chalupsky

Billy K Taylor

Kevan A Lillie

Gopal R Mundada

John J Abbott

Bill Samaras

Pete MacWilliams

Methods and apparatus for Ethernet auto-negotiation (AN) with parallel detect for 10G DAC or other non-auto-negotiated modes. AN base pages are transmitted from an Ethernet apparatus to advertise the ability to support at least one Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet specification supporting AN. A receiver and associated processing circuitry is configured to perform two detection modes in parallel, including a first detection mode that looks for a valid signal transmitted from an Ethernet link peer that does not support AN and a second detection mode looking for AN pages from an IEEE 802.3 Ethernet link peer that supports AN. If the link peer does not support AN, an Ethernet link is set up to use signaling in accordance with the Ethernet specification that does not support AN. If the link peer supports AN, an Ethernet link is set up using a corresponding IEEE 802.3 Ethernet link supporting AN. Supported non-AN Ethernet links include 10G DAC links.

Ethernet auto-negotiation with parallel detect for 10G DAC or other non-auto-negotiated modes

One embodiment provides a network device that includes PHY circuitry comprising transmit circuitry (Tx) and receive circuitry (Rx), wherein the Tx and Rx circuitry are configured to be coupled to a respective channel to communicate with an external device via the channels, wherein the network device configured to communicate with the external device using an Ethernet communications protocol; and test circuitry. The test circuitry is configured to: designate a through channel and at least one crosstalk channel from among the channels; determine, in the time domain, an approximate available signal voltage of a first response signal, wherein the first response signal is in response to a test signal applied to the through channel; determine a first noise profile of the first response signal in response to the test signal applied on the through channel; determine a second noise profile of a second response signal, wherein the second response signal is in response to the test signal applied on a crosstalk channel and measured on the through channel; and determine a signal-to-noise ratio of the through channel based on, at least in part, the approximate available signal voltage and the first and second noise profiles.

Determining the signal quality of an electrical interconnect

Examples are disclosed for characterizing a transmission line. Sets of scatter parameters (s-parameters) associated with measured or modeled insertion loss (IL) or return loss (RL) values over a range of frequencies may be acquired for a transmission line. One or more parameter values for use in IL or RL fit functions may be adjusted to reach a threshold for a coefficient of determination (R) value of a curve generated using the IL or RL fit functions to approximate the set of s-parameters over the range of frequencies. The IL or RL fit functions may then be used to generate other sets of s-parameters associated with IL or RL values for a recreated model of the transmission line. The other sets of s-parameters may be scaled to characterize transmission lines of various lengths. Other examples are described and claimed.

Techniques for characterizing a transmission line

Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802.3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes.

Device communication techniques

Techniques are described that can be used to extend the data transmission rate specified by 10GBASE-KR of IEEE 802.3ap (2007) to more than 10 Gb/s using a multiple lane backplane. A signal for transmission over 10 Gb/s can be divided into multiple streams for transmission over multiple lanes. Multiple transceiver pairs can be used for transmission and receipt of the multiple streams. Each transceiver pair may comply with 10GBASE-KR of IEEE 802.3ap (2007).

Interconnection techniques

Cable interconnection techniques

In one embodiment, the present invention includes a method communicating control information for an external adaptive equalization process for a channel coupled between a transmitter and a receiver from an external agent. In this way, the external agent may control tap settings of an equalizer based on feedback information from the receiver responsive to a data pattern generated and transmitted by the transmitter. Other embodiments are described and claimed.

Performing adaptive external equalization

In some embodiments, an circuit card includes an electronic circuit substrate, a ground plane on the electronic circuit substrate, first and second differential signal pads on the electronic circuit substrate, a ground return signal pad associated with the first and second differential signal pads, the ground return signal pad being connected to the ground plane on the electronic substrate, and a cutout structure on the ground plane positioned near a location where the ground return signal pad connects to the ground plane, wherein the cutout structure is configured to direct a ground return path associated with the first and second differential signal pads to the ground return signal pad associated with the first and second differential signal pads. Other embodiments are disclosed and claimed.

Connector having a cut-out for reduced crosstalk between differential conductors

A method and apparatus for converting skew in a received signal to a low frequency voltage. A signal is received at a destination node from an original signal from a source node. A unity time-voltage sawtooth ramp signal is created at the destination node. The amplitude of the unity time-voltage sawtooth ramp signal is a value in voltage proportional to a pulse width value of the original signal. The unity time-voltage sawtooth ramp signal starts just before the start of the received signal. A skew time is measured from the start of the unity time-voltage sawtooth ramp signal to a threshold level on an edge of the received signal. The measured skew time is correlated to a voltage level on the unity time-voltage sawtooth ramp. The measured skew time for each edge is converted into a pulse where the voltage level of each pulse being proportional to the measured skew.

Method and apparatus for measuring data timing using unity time-voltage sawtooth ramps

An apparatus includes a circuit and a signal source to supply a trigger signal to the circuit. The signal source is adapted to supply the trigger signal such that a reflection of the trigger signal delays the time at which the circuit is triggered.

Method and apparatus to delay circuit trigger

A transmission line for a clock input for a digital device. In the prior art, a clock signal was fed to a digital device on a transmission line. It was found that, when the clock frequency was doubled, the clock pulses received by the device became unacceptable. The invention lengthened the transmission line, rather than shortening it, and thereby removed the unacceptable features of the clock pulses.

Transmission line for high-frequency clock

A branched transmission line, used for delivering control signals to integrated memory circuits. Memory circuits require control signals, which are delivered on control lines. If multiple memory circuits are involved, multiple control lines are used. If the multiple control lines branch from a common branch point on a supply line, undesirable reflections can occur. The invention reduces the reflections, by distributing the branching, as by starting with three initial branches, each of which branches into three other branches, in order to feed nine memory circuits.

Transmission line system for printed circuits

A clock for digital devices. Ordinarily, when multiple digital devices are clocked by a common clock, the clock signals frequently arrive at the digital devices at different times, due to propagation delays. The devices are thus not clocked synchronously. Under the invention, the multiple devices are connected to a common transmission line. A standing wave is generated on the transmission line, and the periodic collapse of the standing wave is used to clock the devices. Synchronous clocking to within about 1.0 nano-seconds has been attained, in a transmission line about ten feet long, wherein a clock signal ordinarily takes about 15 nanoseconds to travel from one end to the other.

Growing community of inventors

Prosperity, SC, United States of America

Richard I Mellitz