Qualcomm Incorporated

Other

Laserscapes LLC

Richard Higgins

Jian Wei

Gilbert Christopher Sih

De Dzwo Hsu

Albert Scott Ludwin

Charles E Sakamaki

Inyup Kang

Tao Li

Sanjay K Jha

Gwain Bayley

Nicholas K Yu

Raghu Sankuratri

Mehraban Iraninejad

Safi Khan

Randy D Jackson

Julio Arceo

Mike E Ring

Bruce R Meagher

Robert W Martin

Michael Koulermos

Robert M Vandeberg

Moto Oishi

Jalal Husseini

Brian Rodrigues

Rachel Higgins

Guanming Shi

Magdy A El-Sabaie

Firdausi D Irani

Duane E Otter

Chauhung Lee

The exemplary embodiments disclosed herein provide a light diffraction device positioned adjacent to a wall and comprising a laser and a diffractive imaging element. The diffractive imaging film having an image and positioned relative to the laser so as to create a projection of the image upon the wall. The diffractive film can also contain a series of images where the film is moved relative to the laser in order to create an animation effect upon the wall. In some embodiments, a distortion reflector may be positioned to accept the laser light exiting the diffractive imaging film and to distort the laser light to produce a desired image upon the wall. In some embodiments, additional reflectors may be used and in some further embodiments a distortion lens may be used.

Light diffraction device

A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

Cached memory system and cache controller for embedded digital signal processor

The dual microprocessor system includes one microprocessor configured to perform wireless telephony functions and another configured to perform personal digital assistant (PDA) functions and other non-telephony functions. A memory system and a digital signal processor (DSP) are shared by the microprocessors. By providing a shared memory system, data required by both data microprocessors is conveniently available to both of the microprocessors and their peripheral components thereby eliminating the need to provide separate memory subsystems and further eliminating the need to transfer data back and forth between the separate memory subsystems. By providing a shared DSP, separate DSP devices need not be provided, yet both microprocessors can take advantage of the processing power of the DSP. In a specific example described herein, the microprocessors selectively program the DSP to perform, for example, vocoder functions, voice recognition functions, handwriting recognition functions, and the like.

Mobile communication device having dual micro processor architecture with shared digital signal processor and shared memory

Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage units, and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.

Direct memory swapping between NAND flash and SRAM with error correction coding

A backpack which includes a main bag, suspension system, frame, and additional miscellaneous parts. It combines the superior comfort of external frame backpacks, with the elegant style of internal frame backpacks. The frame is strapped within the main bag to create a semi-rigid surface against the back. The suspension system's shoulder harness is removable, and adjustably connected through the semi-rigid surface by screws. The shoulder harness is vertically adjustable and swivels to accommodate different shoulder widths. The suspension system's waist harness is removable, and rigidly connected through the semi-rigid surface by screws. The waist harness provides optimum weight transfer onto the hips and creates an air gap, providing ventilation to the back. By removing the frame and placing a cover on it, a seat is formed. By aligning the seat linearly with additional feet, and inserting elongated rails between them, a frame for a cot is formed.

Backpack frame, suspension, seat and cot

The virtual device architecture provides physical and logical device drivers for interfacing software programs executing on a microprocessor of the mobile telephone of a wireless communication system with any of a wide variety of hardware devices connectable within the mobile telephone. The logical device drivers convert commands received from the software applications to commands appropriate for use by selected hardware devices. The physical device drivers receive the converted commands from the logical device drivers and in response to the received commands directly control the selected hardware devices. In one example described herein, the logical device drivers provide translation of core commands necessary to control the selected hardware devices and extended commands for enhanced control of the hardware devices. The logical device drivers operate to convert the extended commands into core commands prior to forwarding the commands to the physical device drivers. By providing logical and physical drivers for use with peripheral devices, the need to provide different versions of software executing on the microprocessor to accommodate different types of peripheral devices is substantially eliminated resulting in a considerable reduction in time and cost associated with developing, maintaining and upgrading software. By providing logical device drivers capable of accommodating both core commands and extended commands, a rich set of peripheral commands can be accommodated thereby further reducing or eliminating the need to provide different versions of software executing on the processor, while nevertheless exploiting the full capabilities of a wide variety of peripheral devices, including state of the art hardware devices such as bit-mapped displays, pointer devices and the like. Method and apparatus embodiments are described.

Virtual device architecture for mobile telephones

An instrumented wheelset system and method for providing an accurate and integrated instrumented wheelset on a train or other vehicle is provided. A subject wheelset is profiled and subjected to finite element analysis. Simulated loading of the wheelset is used to help determine suitable target locations on the wheelset surface for placement of strain sensors. Simulated output of the strain sensors so positioned is recorded to develop wheel sensitivities, without inaccuracies due to strain sensor output ripple and crosstalk. The strain sensors are installed based on the modelled characteristics, and subjected to methodical calibration on a calibration fixture. After any adjustments, the wheelset may be installed on a vehicle including a computer and intelligent data acquisition units for gathering wheelplate data on a live-rolling, realtime basis.

Instrumented wheelset system

Growing community of inventors

San Diego, CA, United States of America

Richard Higgins