Texas Instruments Corporation

Richard H Scales

Jerald G Leach

Kenneth L Williams

Michael J Moody

Jeffrey R Quay

Jonathan G Bradley

Jason AT Jones

Laurence RJr Simar

A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ('ALU') L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. The microprocessor can execute an instruction which shifts a source operand a specified number of bits and saturates the result if a numerical overflow would result from the shift. Execution unit S1 has circuitry for saturating a destination operand by setting all bits within the destination to represent a most positive or a most negative number in a same single instruction execution phase in which the shift would have occurred if not for the overflow. The saturation circuitry examines the source operand prior to shifting to determine if the destination should be saturated.

Method and apparatus for performing a shift instruction with saturate by

A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ('ALU') L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. Execution unit M1 has circuitry for multiplying two operands, shifting the resulting product and saturating the product if an overflow is detected in two execution phase of an instruction execution pipeline.

Microprocessor with an instruction for multiply and left shift with

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Richard H Scales