Intel Corporation

Richard H Livengood

Paul Winer

Valluri Ramana Rao

Michael DiBattista

Jeffrey K Greason

Gary Leonard Woods

Stefan Rusu

Simon M Tam

Darren Slawecki

Steve Seidel

Valuri R M Rao

Suresh Ramalingam

Tak Ming Mak

Elizabeth B Varner

Randall C White

A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.

Method and apparatus for controlling material removal from semiconductor substrate using induced current endpointing

A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the interconnect through vias disposed in a dielectric layer. The combination of the modifiable circuit structure, the interconnect portions, and the vias provide a signal path between transistors in an integrated circuit. In one embodiment the modifiable circuit structure is a polysilicon feature formed over regions of a semiconductor substrate. In an alternative embodiment, the modifiable circuit structure is a diffusion region formed in regions the semiconductor substrate.

Transistor-level signal cutting method and structure

Nano-machining for circuit edits through the front side or backside of an integrated circuit may be performed using a scanning probe system. The system may create access holes with smaller dimensions and facilitate nano-machining endpoint detection in some embodiments.

Physical nano-machining with a scanning probe system for integrated circuit modification

A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the interconnect through vias disposed in a dielectric layer. The combination of the modifiable circuit structure, the interconnect portions, and the vias provide a signal path between transistors in an integrated circuit. In one embodiment the modifiable circuit structure is a polysilicon feature formed over regions of a semiconductor substrate. In an alternative embodiment, the modifiable circuit structure is a diffusion region formed in region the semiconductor substrate.

In one embodiment, the present invention includes a method. In the method, a fiducial transistor is provided in an integrated circuit. Also in the method, a power conductor is coupled to a first terminal of the transistor. Also in the method, a ground conductor is coupled to a second terminal of the transistor. Also in the method, a control conductor is coupled to a third terminal of the transistor. Also in the method, other circuitry is provided, the other circuitry is operatively decoupled from the fiducial transistor and the other circuitry is operable without the fiducial transistor.

Fiducial transistor in an integrated circuit

An integrated circuit device is disclosed. The device comprises a die that has functional units on a first surface and a cooling system arranged adjacent a second surface opposite the first surface. The cooling system comprises a least one microchannel to contain a cooling liquid and to allow flow of the cooling liquid and at least one reservoir arranged adjacent to a region of the die. There is at least one valve between the reservoir and the microchannel to allow the cooling liquid to flow into the reservoir wherein flow of the cooling liquid depends upon a temperature of the die region.

Localized backside chip cooling with integrated smart valves

Method and apparatus for controlling material removal from a semiconductor substrate using induced current endpointing

Method and apparatus for making and using a beacon fiducial for an integrated circuit

In one embodiment, the present invention includes a method including the following acts. A light source is scanned over a surface of an integrated circuit. A photo-induced current is measured from a fiducial in the integrated circuit. The current is correlated to a position of the light source as the scanning progresses.

Method and apparatus for making and using an improved fiducial for an integrated circuit

A capacitor structure is formed on a substrate member having one or more via holes therein. Metallization portions within the via holes of the substrate member form part of the plates of the capacitor.

High performance via capacitor and method for manufacturing same

A backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit. One or more power planes are formed on the backside of the substrate and coupled to power nodes on the front side by deep vias in the substrate. In a specific embodiment of the invention, power planes are coupled through the substrate to front side metal lines, well taps and external connection points. Placing power planes on the opposite side of the substrate from the signal interconnects allows the use of low dielectric constant materials between signal lines, while using high dielectric constant materials between power planes thus increasing decoupling capacitance without increasing parasitic capacitance between signal lines.

Substrate interconnect for power distribution on integrated circuits

A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substrate to send a clock signal to clock an area of the integrated circuit.

Growing community of inventors

San Jose, CA, United States of America

Richard H Livengood