Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Hewlett Packard Enterprise Development LP

Other

Sony Corporation

Richard H Henze

Paul W Poorman

Patricia A Beck

George M Clifford, Jr

Xia Sheng

Gary A Gibson

Zhang-Lin Zhou

Yoocharn Jeon

Charles H McConica

Albert Hua Jeans

Melanie M Gottwals

Ron Roth

Ismail Ari

Stephan P Howe

George Clifford

Bruce F Spenner

Richard Stanley Williams

Warren Bruce Jackson

Jianhua Yang

Gregg Bernard Lesartre

Erik Ordentlich

Naveen Muralimanohar

Martin Foltin

Steven Louis Naberhuis

James A Brug

Si-Ty Lam

Daniel Yves Abramovitch

Hans S Cho

Scott Knudson Anderson

Jeffrey Todd Mabeck

James Ignowski

Yoocham Jeon

Toshiro Ohta

Jeffrey Alan Lucas

Tommy Miles

Terril N Hurst

Carol J Wilson

Francis A Paquette

William L Wilson

Examples disclosed herein relate to a fault-tolerant dot product engine. The fault-tolerant dot product engine has a crossbar array having a number l of row lines and a number n of column lines intersecting the row lines to form l&#xd7;n memory locations, with each memory location having a programmable memristive element and defining a matrix value. A number l of digital-to-analog converters are coupled to the row lines of the crossbar array to receive an input signal and a number n of analog-to-digital converters are coupled to the column lines of the crossbar array to generate an output signal. The output signal is a dot product of the input signal and the matrix values in the crossbar array, wherein a number m&#x3c;n of the n column lines in the crossbar array are programmed with matrix values used to detect errors in the output signal.

Fault-tolerant dot product engine

In example implementations, an integrated characterization vehicle is provided. The integrated characterization vehicle includes a memristor, a configuration cache and an analog measurement tile. The memristor has a driving unit to limit an amount of current that is driven through the memristor during testing. The configuration cache provides test parameters to control the testing of the memristor. The analog measurement tile provides a voltage to the memristor in accordance with the test parameters and to record a response of the memristor.

Integrated characterization vehicles for non-volatile memory cells

A resistive memory device includes a bottom electrode and a top electrode sandwiching a switching layer. The device also includes a field enhancement (FE) feature that extends from the bottom electrode either into the switching layer or is covered by switching layer and that is to enhance an electric field generated by the two electrodes to thereby confine a switching area of the device at the FE feature. The device further includes a planar interlayer dielectric surrounding the device, for supporting the top electrode. A method of making a resistive memory device, employing in-situ vacuum deposition of all layers, is also provided.

Resistive memory device having field enhanced features

A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.

Resistive memory devices with a multi-component electrode

A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.

Non-volatile memory with multiple latency tiers

A memristor device with a thermally-insulating cladding includes a first electrode, a second electrode, a memristor, and a thermally-insulating cladding. The memristor is coupled in electrical series between the first electrode and the second electrode. The thermally-insulating cladding surrounds at least a portion of the memristor.

Memristor devices with a thermally-insulating cladding

A reflective color display has at least a color pixel disposed to receive ambient light for front lighting and has a light source optically coupled to the color pixel to provide back light for backlighting. The color pixel has a first sub-pixel and a second sub-pixel. The first sub-pixel has a first luminescent layer with a luminescent material for converting a portion of the ambient light spectrum into light of a first color. An unpatterned mirror is disposed under the luminescent layer of the first sub-pixel and extends through the first and second sub-pixels. The unpatterned mirror reflects at least light of the first color while transmitting the back light to the first luminescent layer for conversion by the first luminescent material into light of the first color.

Reflective color display with luminescence and backlighting

A display includes at least two stacked waveguides () and (). A first waveguide () contains first luminophores that fluoresce to produce light of a first color. A second waveguide () overlying the first waveguide and contains second luminophores that fluoresce to produce light of a second color. A light collection structure () transmits light from a surrounding environment transversely through the first and second waveguides () and optical vias () provide optical paths out of the display for light respectively from the first optical waveguide () and the second optical waveguide ().

Luminescent stacked waveguide display

A memristor structure has two electrodes sandwiching an insulating region, and includes a nanoparticle providing a conducting path between the two electrodes, wherein either the insulating region comprises an inorganic material and nanoparticle comprises a solid nanoparticle or a core/shell nanoparticle or the insulating region comprises an inorganic or organic material and the nanoparticle comprises a core/shell nanoparticle.

Nanoparticle-based memristor structure

A display element comprises a cell containing a fluid including a plurality of wells at the bottom of the cell. A luminescent material is within the cell for modulating light incident from the top of the cell and for returning luminescent light; and a dispersion of particles is contained within the fluid. The dispersion of particles is movable between a first state in which the particles are substantially contained within the plurality of wells and a second state in which the particles are distributed between the top and bottom of the cell, to control the intensity of luminescent light returned by the display element.

Reflective display

A number of accesses of a portion of data at a first storage device is accumulated. The number of accesses is periodically decremented by a predetermined amount. Based at least in part on the number of accesses, it is determined whether the portion of data of is a candidate for migration to a second storage device.

Method for managing data storage

Methods and systems for providing an alternative caching scheme at the storage area network level are disclosed. In one embodiment, it is determined that the number of accesses to a portion of data associated with a storage device exceeds a threshold that is greater than one access. A copy of the portion of data is associated with a caching resource that provides auxiliary caching for the storage device. The auxiliary caching resource is at the storage area network level. The copy of the portion of data is accessed instead of the portion of data for subsequent accesses.

Providing an alternative caching scheme at the storage area network level

Electronic inks are disclosed herein. The electronic ink includes a non-polar carrier fluid, a plurality of positively charged colorant particles dispersed in the non-polar carrier fluid, and a plurality of reverse co-micelles including a basic charge director and an acidic charge controlling agent. The basic charge director has a molecular weight that is within 5000 of a molecular weight of the acidic charge controlling agent.

Electronic inks

An electrophoretic cell and methods of switching an electrophoretic cell and moving charged species in an electrophoretic cell employ differential electrophoretic mobilities and a time-varying electric field. The methods include providing first and second charged species that are oppositely charged and have different mobilities. The method of switching further includes inducing a net motion of both of the charged species using the time-varying applied electric field. The induced net motion results in either the first charged species being moved toward the electrode and the second charged species remaining essentially motionless or both of the charged species being moved toward the same electrode. The electrophoretic cell includes the first and second charged species with opposite charge and different mobilities, and further includes the time-varying applied electric field that provides the net motion of the charged species.

Electrophoretic cell and method employing differential mobility

Growing community of inventors

San Carlos, CA, United States of America

Richard H Henze