Alcatel Lucent

Alcatel Canada Inc.

Richard Grieve

Dion Pike

Mark R Megarity

James Michael Schriel

Aaron Maxwell MacDonald

Jason T Sterne

Joey Chow

Joey M W Chow

John Madsen

Robert John Johnson

A method of reducing overhead for datagrams that are transmitted to or received from a serial link that reduces overhead to no more than four bytes. The datagram includes at least a Protocol Data Unit (PDU) field, a Start-of-PDU Header (SPH) field, and a SPH Control (SCH) field. The SPH and SCH fields consist of two bytes. The datagram may additionally include End-of-PDU Header (EPH) and EPH Control (ECH) fields. A method may also involve substitution of flags for subsequent headers that are identical to previous headers.

Multi-purpose PDU container for delineating PDU datagrams and PDU datagram attributes in an 8B/10B coded system

A method for incorporating a queuing device as a lossless processing stage in a network device in a communications network, comprising: monitoring a depth of a queue in the queuing device, the queue for receiving packets from an upstream device within the network device, the queuing device acting as a discard point by discarding packets when the queue is full; and, if the depth passes a predetermined threshold, sending a message to the upstream device to reduce a rate at which packets are sent to the queuing device to prevent the queue from filling and thereby preventing packet discarding and loss by the queuing device.

Method and system for using a queuing device as a lossless stage in a network device in a communications network

A circuit comprises two or more chains of components, each chain comprising a plurality of components serially connected by designated pins on each component and at least one chain including one or more components of another chain, the designated pins being designated for data for one or more specific purposes. A selector is included for selecting one chain from the two or more chains over which to data is to be sent. Another circuit comprises a chain of components serially connected by designated pins on each component, and two or more controllers, each controller capable of controlling the chain for one or more of the specific purposes. A wiring board for implementing the circuit is also provided.

Flexible JTAG architecture

A method for incorporating a non-redundant component in a redundant system in a communications network, the redundant system having first and second redundant components providing first and second data streams and activity signals, respectively, the activity signals indicating which of the first and second data streams is an active data stream, the first and second data streams being unsynchronized, the method comprising: determining whether an activity switch has occurred from the activity signals; responsive to the determining, selecting an input data stream from among the first and second data streams; filtering the selected input data stream to produce an output data stream by nullifying any incorrect control information inserted into a packet in the input data stream due to the selecting; and, providing the output data stream to the non-redundant component.

Method and system for incorporating non-redundant components in a redundant system in a communications network

A method and apparatus are provided for storing the boot configuration PROM of a microprocessor in an FPGA. The boot interface of the microprocessor, such as an I2C interface, leads to the FPGA instead of to a PROM. The boot configuration is stored as an image in the FPGA, and the microprocessor accesses the boot configuration using its normal boot interface. In this way, a dedicated boot PROM is not needed, saving real estate on the card on which the microprocessor is located. The boot configuration is also more easily modified, such as for version upgrades or diagnostics, than if the boot configuration were stored on a dedicated PROM. Different boot configurations may be stored as software images on a separate housekeeper processor, for loading into the FPGA.

Implementing a microprocessor boot configuration prom within an FPGA

A signalling system providing communications between a controller and a remote unit in a network element is provided. The signalling system comprises a first communication module associated with the controller, a second communication module associated with the remote unit and a communication link for the first and second communication modules. The first communication module generates a command signal and a downstream monitoring signal for the remote unit. The second communication module receives the command signal and the downstream monitoring signal and generates the status signal and the upstream monitoring signal. The communication link carries the signals. The first communication module monitors for receipt of the upstream monitoring signal and the status signal and determines status of the communication link and the remote unit utilizing results of monitoring for the receipt of the upstream monitoring signal, the status signal and the command signal.

Growing community of inventors

Ottawa, Canada

Richard Grieve