Altera Corporation

Foundry Networks, Inc.

Richard Grenier

Michael David Hutton

Yuen Fai Wong

Yu-Mei Lin

Arifur Rahman

Chee Hak Teh

Carl Ebeling

Arif Rahman

Anargyros Krikelis

Embodiments of the present invention provide tightly coupled off-die memory along with an interface bus and smart buffer logic so as to efficiently perform certain frequent or repetitive operations off of a core logic. Embodiments of the present invention relieve the core logic from performing certain repetitive or frequent memory accesses and other operations so as to allow such core logic to perform other more general or varied operations. In this way, the universal interface bus, smart buffer logic, and off-die memory are specially configured to perform certain select frequent and repetitive operations while the core logic may configured to perform other operations so as to provide an improved configuration with increased computational capability and reduced power budget.

Apparatus and method for fast-path memory operations

An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, a processing circuit, and a configurable control circuit. The configurable storage block may receive an instruction which may be decoded in the control block to identify a command. The command may be associated with a pre-defined sequence of operations that the control block executes by directing the memory array to perform memory access operations and the processing circuit to execute data processing operations. These data processing operations may be executed on data retrieved during memory access operations, data received subsequent to receiving the instruction, or previously computed data. The processed data may be provided for further processing outside the configurable storage block or stored in the memory array. The configurable storage block may further have delay blocks to allow for delayed memory access to the memory array.

Configurable storage circuits with embedded processing and control circuitry

A scalable circuit architecture for programmable circuitry is provided. Intellectual property (IP) blocks may be integrated into a circuit design and may be formed next to programmable logic sectors on which user logic functions are implemented. IP blocks may receive configuration data from sub-system managers (SSMs) that serve as a local configuration source for the IP blocks. Configurable endpoints in the IP blocks may be represented by memory mapped addresses that may be decoded by pipeline decoders having delay elements that prevent read data collision. A reroute layer may serve as an interface between IP blocks and one or more programmable logic sectors. The reroute layer may have a higher number of connections at a logic sector interface compared to the number of connections at an IP block interface. An IP block may route clock signals having different frequencies to respective different rows or regions in the programmable logic sectors.

Scalable architecture for IP block integration

An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array and a control circuit. The configurable storage block may receive a mode selection command. The control circuit may determine to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order based on the mode selection command. Thus, the configurable storage block may implement first-in first-cut modules or last-in first-out modules and variations thereof in addition to implementing memory modules with random access.

Configurable storage blocks with embedded first-in first-out and last-in first-out circuitry

A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.

Method and apparatus for aggregating input data streams

An integrated circuit may have circuitry that includes a storage circuit, a processing circuit, and at least one state register to implement a finite-state machine. The storage circuit may store base addresses and output data for each state of the finite-state machine. The storage circuit may further store offset values that are based on the input data to the finite-state machine and the state transition from a current state to a next state caused by the input data. The processing circuit may compute the address of the storage circuit location where the output data of the next state is stored. The computation of this address may depend on the offset value and base address of the current state. The state register may receive the address from the processing circuit, store the address, and perform the corresponding memory access operation on the storage circuit.

Method and apparatus for operating finite-state machines in configurable storage circuits

A multichip package that includes a programmable interposer is provided. Multiple integrated circuits may be mounted on the interposer. Active circuitry may also be embedded in the interposer device to facilitate protocol-based communications, debugging, and other desired circuit operations. The interposer device may include programmable interconnect routing circuitry that serves primarily to provide routing for the different circuits within the multichip package. A design tool may be used to design the interposer device. The design tool may include a standard die footprint library from which standard interface templates can be selected when designing an interposer device that has to communicate various on-interposer integrated circuits. The use of standard die footprints may simplify the design of interposers by enabling a family of devices to interface with a given interposer.

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San Jose, CA, United States of America

Richard Grenier