Lucent Technologies Inc.

Te Connectivity Corporation

Lattice Semiconductor Corporation

Other

Richard G Stuby, Jr

Barry K Britton

Wai-Bor Leung

Ho Trong Nguyen

James A Thompson

Zeljko Zilic

Satwant Singh

Lucian Remus Albu

Gary P Powell

Carolyn W Spivak

Zheng Chen

William B Andrews

Kai-Kit Ngai

Matthew Edward Mostoller

Barry Britton

Ian L McEwen

James F Hoff

Cort D Lansenderfer

Ravikumar Charath

Ju-Yuan D Yang

Don McCarley

Alan Cunningham

A control system is provided including a sensor element mounted to a light fixture having a photocontrol component for sensing an ambient light and a sensor element communication module for contactless communication of sensor data and identifying data relating to an identifying characteristic of the sensor element to a light fixture communication module of the light fixture. The light fixture communication module receives the sensor data and the identifying data. A verification module receives the identifying data to verify compatibility of the sensor element with a light fixture control circuit having a light control module receiving the sensor data for operable control of a lighting element of the light fixture based on the received sensor data.

Local luminaire area control system

A sensor element for a luminaire local area (LLA) control system includes a receptacle connector, a lighting sensor connector, and an environmental sensor connector arranged in a connector stack coupled to each other and stacked on a light fixture. The receptacle connector includes power contacts for electrical connection with power wires for powering the light fixture. The lighting sensor connector is separate and discrete from the receptacle connector and includes a photocontrol component for sensing an ambient light exterior of the sensor element. The environmental sensor connector is separate and discrete from the lighting sensor connector and includes an environmental sensor component for sensing an environmental characteristic other than ambient light exterior of the sensor element for use by the LLA control system.

Sensor element for a local luminaire area control system

A light sensor assembly includes a photocontrol receptacle connector configured to be mounted to a housing, such as of a light fixture. The receptacle connector has a mating interface for mating with a photocontrol sensor connector. The receptacle connector holds contacts at the mating interface for electrical connection with corresponding contacts of the photocontrol sensor connector for controlling the light fixture. The contacts are configured to be electrically connected to power wires of the light fixture. The receptacle connector includes a receptacle connector communication device for wireless communication with the photocontrol sensor connector.

Light sensor assembly having wireless data transfer

An embedded system bus is woven between a plurality of embedded master elements and at least one slave element within the FPGA device, and provides an external processor interface allowing direct access to any of the plurality of embedded slave elements. Using the embedded system bus, any of a plurality of masters may be allowed to program an embedded element, e.g., embedded FPGA logic, whereas conventional FPGAs allowed only a single master (e.g., a processor) to program the embedded FPGA logic. The embedded system bus is a group of signals, typically data, address and control, that connects system elements together and provides a basic protocol for the flow of data. The embedded system bus allows for control, configuration and status determination of the FPGA device. The embedded system bus is preferably a dedicated function available at all times for arbitrated access to allow communication between the various embedded system components.

Field programmable gate array (FPGA) bit stream format

Multi-master multi-slave system bus in a field programmable gate array (FPGA)

A field programmable gate array (FPGA) has an interface circuit that allows signals to be transmitted directly between the FPGA and a processor. The processor interface (PI) of the FPGA enables the processor to access data at any time from either programmable logic of the FPGA or system registers of the PI. The present invention eliminates the need for external intermediate logic previously required to interface an FPGA and a processor.

Field programmable gate array having a dedicated processor interface

The invention provides an input/output (I/O) signaling voltage range discriminator (and corresponding method) which is used to control a configurable logic device such as a configurable I/O buffer in a second electronic circuit in response to a detected signaling voltage range of a first electronic circuit. The discriminator outputs an indication of the signaling voltage range of the first electronic circuit to a configurable I/O buffer enabling it to adapt to the signaling levels used by the first electronic circuit. The I/O buffer, based on the indication provided by the discriminator, can then configure its logic to become tolerant and/or compatible with digital signals transferred to and from the first electronic circuit.

Signaling voltage range discriminator

The present invention provides an integrated circuit having an operating voltage adaptable buffer, capable of operating in different voltage signaling environments, which includes a control circuit that provides a clamping function to the signaling path under prescribed operating conditions and which also reliably biases the p-type transistor substrate voltage of the buffer to the most positive voltage seen by the buffer under all operating conditions occurring on the signaling path, thereby protecting the p-type transistors.

Operating voltage adapting buffer

The FPGA has an array of programmable logic cells (PLCs) surrounded by a ring of programmable input/output cells (PICs). In one embodiment, the pads of each pair of adjacent PICs, as well as internal routing resources of each of the two PICs, are programmably connected to a single global-signal spine, and the spine is programmably connected directly to only half of the perpendicular branches. Each of the branches can then connect to the cells in two adjacent rows/columns of the array to provide a global signal to any of the cells in the array while only using a branch per every two rows/columns of the device. The reduced number of spine-to-branch connections reduces the capacitive loading on the spines, thereby increasing the speed at which global signals can be transmitted. In addition, sharing spines between adjacent PICs reduces the number of spines in the FPGA by half, thereby providing additional layout space for other resources. Sharing branches also has the same effect as sharing spines in that the number of branches is reduced by half, also increasing global signal speed. These advantages are achieved without reducing the programming flexibility of the FPGA.

Global signal distribution with reduced routing tracks in an FPGA

A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can be programmed during PLD operations, without reconfiguring the PLD.

Programmable clock manager for a programmable logic device that can be

A programmable logic device, such as an FPGA, is implemented using logic cells that have configurable connection schemes between routing resources and logic element input pins. For example, in one embodiment, each logic cell in the device has a flexible input structure that supports two or more different connection schemes, which may or may not involve input sharing, where each logic cell can be individually programmed for any of the available connection schemes when the device is configured. As such, the device can be efficiently programmed to implement the user's specific circuitry. The invention balances the competing goals of (1) reducing routing requirements by limiting the number of connections between routing resources and logic element input pins and (2) providing minimally constrained programming of logic elements.

Programmable logic device with logic cells having a flexible input

A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can perform one or more delay-locked loop (DLL) functions. In one embodiment, the DLL functions include clock delay, duty-cycle adjustment, and clock doubling, where duty-cycle adjustment can optionally be applied independently to the doubled clock cycles.

Programmable clock manager for a programmable logic device that can

A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least two different output clocks having different clock rates. The different output clocks can be used to control different processes either within or outside the FPGA. For example, one output clock can be used to control the FPGA's input/output registers, while a second, faster output clock can be used to control the FPGA's internal registers.

The bi-directional (BI-DI) buffers and supplemental logic and interconnect (SLIC) cells are designed to be programmed to operate in different modes in order to implement different kinds of logic circuits. In particular, BI-DI buffers of the present invention support at least five different operational modes. In a first mode (Mode A), the BI-DI buffer generates a logic '1' output, for any input value. In a second mode (Mode B), the BI-DI buffer generates a logic '0' output, for any input value. In a third mode (Mode C), the BI-DI buffer buffers the input signal and generates an output signal equal to the input signal. In a fourth mode (Mode D), the BI-DI buffer buffers the input signal and generates an output signal equal to the inverse of the input signal. In a fifth mode, (Mode E), the BI-DI buffer operates as a conventional tri-state driver. Two or more of the BI-DI buffers can be configured to form more complex logic circuits having two or more inputs. For example, groups of BI-DI buffers can be configured as SLIC cells that are part of the basic logic cells for an FPGA. When used in FPGAs, the BI-DI buffers and SLIC cells make implementation of different kinds of logic circuits more efficient than is the case for conventional FPGAs, including logic circuits like decoders and state machines that have large numbers of inputs. At the same time, the FPGAs retain their efficiencies for implementing logic circuits for which FPGAs have traditionally been very efficient, such as random logic and datapath logic.

Growing community of inventors

New Tripoli, PA, United States of America

Richard G Stuby, Jr