Advanced Micro Devices Corporation

Richard G Russell

David Francis Tobias

Evandro Carlos Menezes

Morrie Altmejd

Mark Tracy Ellis

Gary Michael Godfrey

Lloyd W Gauthier

Donald G Craycraft

Jim Mergard

A computer system has multiple performance states. The computer system periodically determines utilization information for the computer system and adjusts the performance state according to the utilization information. If a performance increase is required, the computer system always goes to the maximum performance state. If a performance decrease is required, the computer system steps the performance state down to a next lower performance state.

Method and apparatus for improving responsiveness of a power management system in a computing device

System and method for controlling an intergrated circuit to enter a predetermined performance state by skipping all intermediate states based on the determined utilization of the intergrated circuit

A microcontroller has many internal peripheral devices. The peripheral devices are coupled to a scan path. A memory storage device that is external to the microcontroller is also coupled to the scan path. When commanded, data is shifted out of each device configuration register onto the scan path and stored in the external memory device. This is particularly useful for obtaining the states of each device without bringing down the application. Furthermore, configuration data stored in external memory can be loaded into the peripheral device configuration registers via the scan path. This invention also supports zero-volt suspend/resume which does not need extra software readable shadow registers which are often required in other architectures for reading back the current state of legacy registers which are read-only.

Method and apparatus for communicating configuration data for a peripheral device of a microcontroller via a scan path

Method and apparatus for saving peripheral device states of a microcontroller

A computer system that has multiple performance states periodically obtains utilization information for a plurality of tasks operating on the processor and determines processor utilization according to the utilization information for the plurality of tasks. The system compares the processor utilization to at least one threshold and selectively adjusts a current processor performance state to another performance state according to the comparison.

CPU utilization measurement techniques for use in power management

A computer system has multiple performance states. The computer system periodically determines if the software power state maintained by power management software that represents the power state of the processor or other computer system component matches the actual power state of the processor or other computer system component. If not, the actual power state and the software power state are resynchronized, for example, by reinitializing the power management software or otherwise causing the software power state to match the hardware power state.

Power state resynchronization

A system is provided that contains multiple control register and descriptor table register sets so that an execution context switch between X86 protected mode operating systems can be performed with minimal processing overhead. Upon receipt of a protected instruction determined to be a meta-protected instruction, the system calls a meta virtual machine (MVM) that performs the functions necessary to shift execution contexts.

Multiple protected mode execution environments using multiple register sets and meta-protected instructions

The scalable virtual timer system or subsystem implements multiple hardware timers with minimal silicon overhead. In one embodiment, for each virtual timer of a plurality of virtual timers, a content addressable memory stores a sum of an &ldquo;initial state&rdquo; of a free running counter and a desired count duration for the virtual timer. When the stored value matches a current state of the free running counter, the content addressable memory generates a terminal count for the virtual timer. In an alternative embodiment, for each virtual timer, a period register of a set of period registers stores a sum of a desired count duration for a virtual timer and an &ldquo;initial state&rdquo; of the free running counter. A comparator of a set of comparators generates a terminal count for a virtual timer when a current state of the free running counter matches the sum stored in a period register associated with the virtual timer. A state of the free running counter may be read through software, such as by an execution unit, or through hardware, such as by an adder.

Scalable virtual timer architecture for efficiently implementing multiple hardware timers with minimal silicon overhead

A system provides pseudo-concurrency for a volatile memory and a non-volatile memory on a same data bus. In one system embodiment, the volatile memory is coupled to its own address bus, and the non-volatile memory is coupled to its own address bus. In another system embodiment, the volatile memory and non-volatile memory are coupled to a multiplexed address bus. Concurrent with an access cycle to the volatile memory, the non-volatile memory may be precharged. After the access cycle to the volatile memory, a data cycle to a non-volatile memory may be executed. Concurrent with an access cycle to the non-volatile memory, the volatile memory may be precharged. After the access cycle to the non-volatile memory, a data cycle to the volatile memory may be executed.

Pseudo-concurrency between a volatile memory and a non-volatile memory on a same data bus

Method and apparatus for saving and loading peripheral device states of a microcontroller via a scan path

A processor-oriented system provides a timer processing engine for supporting multiple virtual minimum time timers. The plurality of virtual minimum time timers of the timer processing engine includes a timer data structure suitable to store timer states of the plurality of virtual minimum time timers. Each timer state may include an elapsed time value, a last time value, a terminal time value, and a set of attributes. The timer states are processed by a timer state machine of the timer processing engine. The plurality of virtual minimum time timers further include a free running counter for providing a current time of the timer processing engine and a comparator for maintaining the timer states. The comparator maintains timer states by performing comparison operations for each virtual minimum time timer. When a virtual minimum time timer reaches a terminal time value, an interrupt generator of the timer processing engine may generate an interrupt.

Timer processing engine for supporting multiple virtual minimum time timers

A general purpose dynamically programmable state engine dynamically executes finite state machines and finite state machine models. The state engine includes an input and filter unit, a storage unit, a transition unit, and an action generation unit. The storage unit stores a state entry table including a plurality of state entries. Each state entry in the storage unit includes a state identifier, a symbol identifier, a plurality of state attributes, and a next state. The input and filter unit accepts inputs and translates the inputs to symbols. The symbols are provided to the transition unit. The transition unit maintains a current state and locates a state entry in the storage unit having a state identifier matching the current state and a symbol identifier matching a current symbol. The current state is set to a next state of a matching entry by the transition unit when the matching entry is a terminating entry. When a terminating entry is detected, an action generation unit for processing the terminating entry is activated. A finite state machine may be configured for execution by the state engine using a state machine development tool.

Growing community of inventors

Austin, TX, United States of America

Richard G Russell