Zenith Radio Corporation

Other

Richard G Merrell

Melvin C Hendrickson

Johnny Collins

David A Blass

Malvin P Pettersen

A television receiver includes a recognition system identifying the 19th horizontal scanning line of each field of a transmitted television signal for coupling a vertical interval reference (VIR) signal to suitable signal processing circuitry within the receiver. The recognition system includes a timing circuit defining a pair of predetermined timing intervals in each horizontal scanning line during which the logical characteristics of the composite sync signal are sampled and interrogated. A counter is advanced to a preselected state in response to the samples exhibiting a predetermined sequence of logical characteristics occurring during the vertical sync pulse and its associated following equalizing pulse interval. Subsequently, horizontal flyback pulses are counted and the output of the counter is decoded for identifying the 19th horizontal scanning line. A carryover circuit is provided for rendering line 19 identifications for fields during which the predetermined sequence is unsatisfied in accordance with the last line 19 identification corresponding to a satisfaction of the sequence.

VIR line recognition system

A television window tuning system has duty cycle adjustment means for selectively varying the duty cycle of the tuner associated local oscillator signal. Increasing the duty cycle of the local oscillator signal effectively shifts the tuning window in frequency space in one direction while decreasing the duty cycle shifts the window in the opposite direction. In one embodiment of the invention, the duty cycle adjustment means is set for producing a 0% duty cycle oscillator signal for deriving a tuning window particularly adaptable for use with conventional AFC systems.

Apparatus for shifting a tuning window

An all-channel PLL tuning system includes LOF counters, a comparator producing an equality pulse each time the LOF count matches a preselected channel number count and a digital phase-frequency comparator comparing the equality pulses with reference pulses. High speed tuning is accomplished with the phase-frequency comparator arranged to yield immediate correct directional information. A reset pulse is generated for every other equality pulse and forces the equality and reference pulses to have the same initial phase and the digital phase-frequency comparator into one of its stable states corresponding to the desired output condition. The output directional information from the phase comparator is stored and tuning proceeds at high speed until a change in directional information occurs, indicating that the correct tuning frequency has been passed. Normal PLL operation then ensues.

High speed phase locked loop tuning system

An electronic television tuning system includes a channel number selection integrated circuit chip interfaced with a channel computer integrated circuit chip by a plurality of data lines. The channel number selection chip, in response to the partial or complete entry of a channel number by the viewer, develops multiplexed digital codes on the data lines representing the channel number entry and, in certain circumstances, a predefined blanking code. A display apparatus, coupled to the data lines, provides an observable indication of the channel number entry, portions of the display being suitably blanked in response to the blanking code. Tuning information and raster blanking signals are developed by the channel computer chip directly from the information supplied on the data lines.

Electronic television tuner interface circuit

Digital phase comparator with reset

A two mode tuning system includes counters for determining system tuning by counting the LOF, a channel number comparator comparing the derived channel tuning information with a desired channel number and a PLL including a phase comparator for comparing equality pulses from the channel number comparator with a reference frequency. In the first mode the system tunes to a single frequency and in the second it tunes within a frequency window. Tuning cycle control means initiate the single frequency mode in response to a channel number input or an out-of-window tuning indication and the system switches to the tuning window mode about 200ms later. Initially tuning to the 'center of the tuning window' relaxes the AFC requirements for a wide window system. The tuning cycle control means also provide for initially overriding the phase comparator and PLL to drive the oscillator at 'full ramp' until system tuning is driven past the frequency corresponding to the input channel number. Then, the single frequency PLL mode is initiated.

High speed tuning system

The disclosure relates to a safety device for use in a garage door opening and closing system of the type which includes an impulse actuated reversible motor which opens and closes the garage door and wherein the safety device automatically actuates the motor for closing the door should the door be inadvertantly opened or accidentally remained open. The safety device includes a detector for detecting the open or closed condition of the door, a counter for keeping time responsive to the detector detecting that the door is open, and a logic circuit for providing repetitive impulses to the motor to actuate the motor for closing the door. The counter terminates keeping time and is reset by the detector when the detector detects that the door is closed. The safety device additionally includes an indicator responsive to the repetitive impulses for indicating that the logic circuits have actuated the motor for closing the door.

Electronic garage door opener safety device

A wireless remote control system has a transducer coupled to a sampling frequency counter to distinguish among various actuating signals. A comparator compares present and immediately preceding measurements and a confidence counter counts the number of identical comparisons and is reset for non-identical comparisons. A decoder which is disabled until the confidence counter reaches a predetermined count is coupled to utilization means to actuate the selected function. Logic means contain a clock controlled interval counter which is activated only after the confidence counter reaches the predetermined count for establishing a timing interval. During the interval logic means render the confidence counter unresponsive to the comparator thereby maintaining actuation of selected functions. Logic means also force a preset count into the interval counter to prevent establishing the timing interval for other functions.

Remote control with reduced responsiveness to interrupted actuating

An all-channel two mode television tuning system includes a counter for sequentially generating channel numbers to adjust tuning. An 82 .times. 1 bit read/write memory is addressed in a program mode by the generated channel numbers to provide locations for storage of signals for tuning to preselected channels. Blanking circuitry responsive to the 60Hz line frequency as a clock source causes repetitive flashing of the channel number indicators until the generated channel number has been stored. In the operate mode channel numbers are again generated to access the memory locations and logic circuitry determines when the generated channel numbers correspond to preselected (stored) channel numbers to provide tuning thereto.

Channel selection indicator for memory tuning system

An electronic all channel television tuning system has a presettable counter for deriving the number of the receivable television channel by counting, on a continuing sample basis, the varactor diode tuner local oscillator frequency. The derived channel number is supplied as an input of a comparator which includes separate tens and units channel number comparison sections. A channel number selector supplies an encoded desired channel number to another input of the comparator and to a frequency band decoder which establishes appropriate preset information for the counter. The system local oscillator frequency is varied by a voltage ramp circuit having two pairs of matched current sources and sinks of different capacity for supplying current, through respective transmission gates, to charge or discharge a tuning capacitor at different rates. A difference in the tens section of the comparator activates the transmission gates for both the larger and smaller capacity source-sink pairs, producing the high ramp speed. After equality in the tens digits only one of the small capacity source-sink pair is activated, under control of the units section of the comparator, to produce the low ramp speed.

Growing community of inventors

Darien, IL, United States of America

Richard G Merrell