D-Wave Systems Inc.

1372934 B.c. Ltd

Richard G Harris

Andrew Joseph Berkley

Paul I Bunyk

Mark W Johnson

Mohammad H Amin

Mohammad H S Amin

Trevor Michael Lanting

Kelly T R Boothby

Jan Johansson

Emile M Hoskinson

Anatoly Smirnov

Jeremy P Hilton

Loren J Swenson

Jed D Whittaker

Christopher B Rich

Andrew Douglas King

Sergey V Uchaykin

Eric G Ladizinsky

Byong Hyop Oh

Colin C Enderud

Douglas P Stadtler

Fabio Altomare

Nicolas C Ladizinsky

Jason J Yao

Shuiyuan Huang

Edward G Sterpka

Jan E S Johansson

Andrew Brock Wilson

Geordie Rose

Aidan Patrick Roy

James King

William W Bernoudy

Jacob Craig Petroff

Chunqing Deng

Rahul Deshpande

Kamran Karimi

Mohammad Amin

Andrew J Berkley

Mark Johnson

Byong H Oh

Systems and methods for measuring noise in discrete regions of multi-layer superconducting fabrication stacks are described. Methods for measuring noise in spatial regions of a superconducting fabrication stacks may include the use of resonators, each having a different geometry. As many resonators as spatial regions are fabricated. Data collected from the resonators may be used to calculate fill fractions and spin densities for different spatial regions of the superconducting fabrication stack. The data may be collected via on-chip electron-spin resonance. The superconducting fabrications may be part of a fabrication stack for a superconducting processor, for example a quantum processor, and the spatial region studied may be proximate to qubit wiring layers.

Systems and methods for on-chip noise measurements

A system and method for mitigating flux trapping in a superconducting integrated circuit. A first metal layer is formed having a first critical temperature and a first device, and a flux directing layer is formed having a second critical temperature. The flux directing layer is positioned in communication with an aperture location, and the aperture location is spaced from the first device to isolate the first device from flux trapped in the aperture. The superconducting integrated circuit is cooled from a first temperature that is above both the first and second critical temperatures to a second temperature that is less than both the first and second critical temperatures by a cryogenic refrigerator. A relative temperature difference between the first and second critical temperatures causes the flux directing layer to direct flux away from the first device and trap flux at the aperture location.

Systems and methods for fabricating flux trap mitigating superconducting integrated circuits

A logical qubit, a quantum processor, and a method of performing an operation on the logical qubit are discussed. The logical qubit includes first and second tunable couplers and a plurality of fixed couplers, with at least one fixed coupler providing four physical qubit interaction. The first and second tunable couplers and the fixed couplers enforce even parity in any connected qubits. The logical qubit has a plurality of physical qubits with qubits connected to the first tunable coupler and a first fixed coupler, qubits connected to the second tunable coupler and a second fixed coupler, and qubits connected between the first fixed coupler and the second fixed coupler. Each fixed coupler is connected to at least two physical qubits and at least two paths connect the first tunable coupler and the second tunable coupler, with one path communicating with a microwave line.

Topologically protected qubits, processors with topologically protected qubits, and methods for use of topologically protected qubits

A system and method of implementing finite element modeling on a quantum processor is discussed. A representation of a computational problem including a boundary value problem and problem grid points is received by one or more processors. The problem grid points are mapped to a Hilbert space of the qubits of the quantum processor. The boundary value problem is transformed into a problem Hamiltonian. Instructions are transmitted to the quantum processor to cause the quantum processor to evolve from an initial state to a final state based on the problem Hamiltonian. The wavefunction amplitudes of the final state are measured, and the wavefunction amplitudes of the final state are mapped onto the problem grid points based on the Hilbert space of the qubits.

Systems and methods for implementing finite element modelling

Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.

Systems and methods for tuning capacitance in quantum devices

Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

Systems, methods and apparatus for active compensation of quantum processor elements

Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

Systems and methods for fabrication of superconducting integrated circuits

Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a 'braided' pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

Systems and methods for superconducting devices used in superconducting circuits and scalable computing

A hybrid computing system for solving a computational problem includes a digital processor, a quantum processor having qubits and coupling devices that together define a working graph of the quantum processor, and at least one nontransitory processor-readable medium communicatively coupleable to the digital processor which stores at least one of processor-executable instructions or data. The digital processor receives a computational problem, and programs the quantum processor with a first set of bias fields and a first set of coupling strengths. The quantum processor generates samples as potential solutions to an approximation of the problem. The digital processor updates the approximation by determining a second set of bias fields based at least in part on the first set of bias fields and a first set of mean fields that are based at least in part on the first set of samples and coupling strengths of one or more virtual coupling devices.

Systems and methods for hybrid analog and digital processing of a computational problem using mean fields

A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body.

Universal adiabatic quantum computing with superconducting qubits

Methods for reducing errors in calibrated devices comprise detecting outliers, self-checking consistency of measurements, tuning device controls to target values, and absolutely calibrating devices via a first standard and cross-checking the results via a second standard. The first standard may be a calibrated current and the second calibration standard may be a calibrated frequency. A calibrated frequency may be a microwave signal applied to the body of a qubit. Qubit annealing controls can quickly lower and raise the tunnel barrier to measures the oscillation frequency of the qubit between two potential wells.

Systems and methods for reducing errors in calibrated devices

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Richard G Harris