International Business Machines Corporation

Richard G Fogg, Jr

Joseph R Mathis

Mark D Sweet

Arturo M De Nicolas

James O Nicholson

John W Irwin

John C O'Quin, Iii

Carl Zeitler, Jr

Joe Wayne Blackard

Arturo M De Nicholas

A host interface for a logic simulation machine for transferring data between the logic simulation machine and a host computer is disclosed. The host interface includes a First-In First-Out buffer provided between the logic simulation machine and the host computer for temporarily storing data being transferred between the logic simulation machine and the host computer until a receiver of the data is ready to receive the data. The host interface minimizes delays due to host interaction with the logic simulation machine during the communication between the host and the logic simulation machine.

Interface for logic simulation using parallel bus for concurrent

The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by utilizing a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions by detecting, at the time of a store to memory, whether an instruction, data, or video is being updated. If the memory location that is being updated contains an instruction, the simulator takes additional steps to guarantee the correct execution of the modified instruction. If the simulator determines at the time of a store that the memory location being modified is data, the simulator needs to take no additional steps.

Memory mapping and special write detection in a system and method for

A DMA controller has an attached, dedicated memory. Data objects are stored on the heap and connected by pointers. Each data object contains DMA block transfer control parameters. A single block transfer made up of several separate transfers, with each separate transfer defined by one data object. The single block transfer is defined by linking several data objects into a list. The DMA controller consecutively performs the transfers in a linked list without requiring control by a system central processor.

System for DMA block data transfer based on linked control blocks

The system and method of this invention allows a simulated processor to receive an interrupt request from I/O devices. A simulated interrupt controller routine determines whether to post an interrupt to the simulated CPU. The simulated interrupt controller routine posts an interrupt to the simulated CPU by updating one byte, which is owned by the simulated interrupt controller, of a two byte halfword. The other byte is owned by the simulated CPU and is updated by the simulated CPU when its internal interrupt enabled state changes. Each byte of the two byte halfword is updated independently, but is loaded by the simulated CPU with only one instruction to determine if an interrupt should be acknowledged. The simulated CPU minimizes the overhead of polling for an interrupt by performing a graph analysis of the instruction flow of control to determine the locations to poll for interrupts. The simulated CPU polls for an interrupt when an instruction transfers control dynamically, once around a loop, and when an instruction changes the interrupt enabled state of the simulated CPU.

System and method for simulating the I/O of a processing system

A memory system that includes several memory locations connected to a reading circuit that provides read access to the memory location. The memory system also includes the controller that receives control information. A writing circuit is further included that provides write access to either only a first portion of the memory locations, or simultaneously several portions of the memory locations is designated by the control information. This invention further includes a memory system that provides several memory locations for the storage of information together with the controller having a first port and a second port. The first port provides access to the memory locations in response to a first address range and the second port provides access to the memory locations in response to several address ranges wherein at least one of the address ranges of the second port is different then the address range of the first port. Still further, the invention includes a memory system having a first group of memory locations that store information in accordance with the first address range and a second group of memory locations. The two groups of memory locations are connected to a controller that provides write access to the first group of memory locations in a response to write commands having addresses within the first address range and, simultaneously writing each write command address in the second group of memory locations.

Data processing system with multi-access memory

In a communications system, a sending system and a receiving system have multiple data buffers. In response to an inquiry from the sending system, the receiving system transmits information which indicates the size and number of data buffers available in the receiving system. The sending system then begins transmitting data frames, which are placed into the buffers of the receiving system. When the receiving system removes all of the data from a buffer, therefore freeing it to accept additional data, it sends a signal to the sending system indicating this fact. The sending system counts such signals, and ensures that the number of transmitted data frames does not exceed the number of frames which have been removed from the receiver's buffers by more than the number of buffers which the receiver has.

System and method for data communications

The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by utilizing a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions by performing a graph analysis on the application's instruction flow of control to determine which condition codes of each instruction are not needed for a subsequent instruction. Fewer translated instructions are needed if the condition codes for an instruction are not set or used subsequently.

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Austin, TX, United States of America

Richard G Fogg, Jr