International Business Machines Corporation

Richard G Eikill

Sheldon Bernard Levenstein

Charles Porter Geer

Quentin G Schmierer

Lynn Allen McMahon

Steven J Finnes

Joseph P Weigel

A data processing network includes multiple processing devices, multiple memory cards of main storage, and a shared interface. Each of the memory cards includes memory arrays, an internal register for temporarily storing a pointer data word read from the arrays, and logic circuitry. When one of the processing devices sends a tag bit extraction or tag bit insertion command to one of the memory cards, the pointer to be modified is retrieved from a selected address in the memory arrays and latched into the internal register. The logic circuitry provides the tag bits to an AND logic gate and provides the AND gate output to the processor in the case of tag bit extraction. For tag bit insertion, the circuitry applies the pointer from the arrays and a tag bit input from the processor, as inputs to a multiplexer and provides the multiplexer output back to the selected address in the arrays.

Logic on main storage memory cards for insertion and extraction of tag

An information processing network includes multiple processing devices, a main storage memory, one or more disk drives or other auxiliary storage devices, and an interface for coupling the processing devices to the main storage memory and the auxiliary devices. A primary directory in main storage contains mapping information for translating virtual addresses to real addresses in main storage. Look-aside buffers in the processing devices duplicate some of the mapping information. A primary directory hardware lock, subject to exclusive control by any one of the processing devices to update the primary directory, inhibits access to the primary directory based on hardware address translations initiated when one of the processors holds the primary directory lock. Address translations in progress when the lock is acquired proceed to completion before the primary directory is updated under the lock. Accordingly, such updates proceed atomically relative to hardware primary directory searches. Unnecessary quiesces and purges of the look-aside buffers are eliminated, substantially improving network performance.

Hardware primary directory lock

A data processing network includes multiple processing devices, multiple memory cards of main storage, and a main storage interface shared by the processors and memory cards. Each of the memory cards includes memory arrays, a hold register for retaining a data pattern stored to the arrays, a compare register and logic circuity. For a memory array diagnostic test, one of the processing devices sends a compare command (including address information) and the data pattern to one of the memory cards. In response, the logic circuity on the selected memory card stores the data pattern to its hold register and writes the data pattern into its memory arrays, then reads the data out of the memory arrays into its compare register. The contents of the compare and hold registers are compared, and an error indication provided to the processing device in the event that these registers' contents are not the same.

Memory card resident diagnostic testing

A fast store-through cache process is disclosed in connection with multiple processors sharing a main storage memory. Each processor has a cache memory including multiple cache lines, each line associated with an address in main storage. Each cache memory has a cache directory for recording main storage addresses mapped into cache memory, identifying cache lines as valid or invalid, and holding status bits of data words stored in the cache memory. According to the process, a data word is stored in the cache memory during a first clock cycle and the associated cache directory is read to determine whether the corresponding main storage address is mapped into the cache memory. If so, and if no status bits in the data word require update, the store to the cache memory is complete. If a different main storage address is mapped into the cache memory, processor logic generates a processor interrupt signal during the second clock cycle, and the processor is interrupted during the third clock cycle while the cache directory is modified to purge the corresponding cache line. If the main storage address is in the cache memory but the data includes at least one status bit requiring update, the interrupt signal is generated during the second clock cycle, with the cache directory modified to update status bits during the third clock cycle. Special logic forces modifications to the cache directory if two consecutive store or fetch operations correspond to the same location in main storage.

Fast store-through cache memory

A data processing network includes multiple processing devices, one or more memory cards in main storage, and a shared interface for processor access to main storage. Each of the memory cards includes dynamic random access memory arrays which require a periodic refresh pulse. To provide refresh pulses, each of the memory cards includes a programmable register, a counter receiving clock pulses, and a comparator. The comparator generates a request pulse each time the output from the pulse counter equals a selected value provided by the register. The register is programmable to controllably adjust the selected value, and thus select the frequency at which refresh request pulses are generated by the comparator. The memory card further includes a buffer for receiving the refresh request pulses and generating a refresh request responsive to each pulse. Responsive to the refresh request, a memory array control circuit either provides a refresh signal to the arrays, or stores the refresh request, depending on whether the arrays are busy with an external request. However, when stored requests accumulate to a predetermined threshold, the external request is interrupted and a refresh signal is provided to the arrays.

Memory card refresh buffer

A data processing network includes multiple processing devices, multiple memory cards of main storage, and a shared interface. Each of the memory cards includes memory arrays, an internal register for temporarily storing a data word read from the arrays, and logic circuitry. When one of the processing devices sends a set or reset command to one of the memory cards, the processor also sends a data mask. A data word to be modified is retrieved from a selected location in the memory arrays and latched into the internal register. The logic circuitry applies the data mask to a data word in the internal register, to modify the data word according to the data mask, then returns the data word to the selected location in the arrays.

Data processing system and associated process using memory cards having

A high performance interface joins multiple processing devices configured as masters, with multiple memory cards or other devices configured as slaves. The interface includes a working data bus for transmitting working information between the processors and memory cards. Auxiliary busses, including a command/address bus for commands and address information and a communication bus for status information, are connected to all of the processing devices and slave devices and operate in parallel with the working data bus. A system for distributing control of the working information bus, among all of the master devices and slave devices, includes a grant token and plural select tokens. The grant token, a line connected in common to all devices, permits a device currently controlling the interface to retain control until it completes its transmission. The select tokens, each connected to a uniquely associated slave device and to all of the master devices, consists of a command active line activated by a master device when providing a store or fetch command, a return data line activated by a selected master device to retrieve earlier requested data from a selected slave device, and a buffer full line whereby a slave device with its buffer occupied communicates this fact to all of the master devices. Store and fetch operations are conducted according to command transfer and return data transfer protocols, which optionally include an acknowledgement via the communication bus that a command was received during the next preceding clock cycle.

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Rochester, MN, United States of America

Richard G Eikill