Freescale Semiconductor,inc.

Nxp Usa, Inc.

Richard G Collins

William C Moyer

Jason T Nearing

Zheng Xu

Michael D Fitzsimmons

Suraj Bhaskaran

John H Arends

Brian Christopher Kahne

James C Holt

Jonathan J Gamoneda

John J Kim

An approach is provided in which an endianness violation detection sub-system detects endianness violations between hardware units. The endianness violation detection sub-system tracks memory operations performed by multiple hardware units via debug channels and generates lookup table entries that are stored in a lookup table. When the endianness violation detection sub-system detects endianness relevant load attributes of a load operation that are different than corresponding endianness relevant store attributes of a store operation, the endianness violation detection sub-system generates an endianness violation. In one embodiment, the endianness violation detection sub-system identifies an endianness violation when the endianness violation detection sub-system detects a difference in the byte ordering type between a hardware unit performing a store operation and a hardware unit performing a load operation.

Detecting byte ordering type errors in software code

In one or more embodiments, a data processing system can include at least one core capable of executing instructions of an instruction set architecture and a trace unit coupled to the at least one core. A call to a subroutine can be detected, and in response, a program trace correlation (PTC) message can be generated and sent to a trace port. Data associated with an execution of the subroutine and/or performance of the data processing system can be sampled and sent to the trace port. A return from the subroutine can be detected, and in response, a trace message can be generated and sent to the trace port. The PTC message and the trace message can be correlated, and the correlation of the PTC message and the trace message can be used to determine a boundary for the subroutine and/or the sampled data associated with the execution of the subroutine.

Trace correlation for profiling subroutines

A data processing system has a trace message filtering circuit. A method includes: receiving a current page address corresponding to a current instruction in a sequence of instructions; determining that the current page address is for a different page of memory than a previous page address corresponding to a previous instruction in the sequence of instructions; comparing the current page address with a plurality of page addresses stored in a message filtering circuit; and when the current page address is determined to be different than any of the plurality of page addresses, storing the current page address in the message filtering circuit.

Program trace message generation for page crossing events for debug

A data processing system and method generates debug messages by permitting an external debug tool to have real-time trace functionality. A data processor executes a plurality of data processing instructions and uses a memory for information storage. Debug module generates debug messages including address translation trace messages. A memory management unit has address translation logic for implementing address translation to translate addresses between virtual and physical forms. The debug module includes message generation module that is coupled to the memory management unit for receiving notice when one or more address translation mappings are modified. The message generation module generates an address translation trace message in response to a detection of a modification of an address translation mapping occurs and provides the address translation trace message external to the debug module.

Address translation trace message generation for debug

A method of generating timestamped trace messages includes generating a trace message in response to an event at an instruction pipeline of a data processing device. If timestamping is enabled, timestamps are only included in the trace message only if a programmable condition is detected. For example, a timestamp can be included in the trace message if the amount of space used to store messages at a trace message buffer exceeds a watermark value. The condition that results in a timestamped trace message is programmable, and can be selected via a debug interface. Because timestamps are only included in trace messages when the programmable condition is satisfied, some trace messages will not include a timestamp, thereby reducing the amount of buffer space needed to store the trace messages.

Trace messaging device and methods thereof

A data processing system having debug message generation uses processor circuitry to perform a plurality of processor operations. Global control circuitry is coupled to the processor circuitry. Debug circuitry is coupled to the global control circuitry for generating debug messages corresponding to predetermined processor operations. Message generation logic provides debug messages which selectively include a timestamp field providing information as to when a debug message is generated. Debug control circuitry is coupled to the global control circuitry and the message generation logic and has a timestamp control register. For each of a plurality of debug message types, the timestamp control register selectively enables or disables appending a timestamp to the debug message for that type of debug message. Enable logic is coupled to the timestamp control register for enabling or disabling the timestamp control register based on detecting a selected event in the data processing system.

Debug messaging with selective timestamp control

A data processing system and method includes a data processor and memory that are coupled to debug circuitry that generates debug messages including address translation trace messages. A memory management unit (MMU) includes a translation lookaside buffer (TLB) for implementing address translation to translate addresses between virtual and physical forms. The debug circuitry includes message generation circuitry coupled to the MMU for receiving notice when TLB entries are modified and generating both an address translation trace message and a corresponding program correlation message containing at least one of branch history information and instruction count information. The branch history information is a history of direct branch instructions that are executed and whether, when executed, the direct branch instructions were taken. The instruction count information is a count of one or more data processing instructions executed up to a point in time when a new TLB entry is established in the TLB.

Program correlation message generation for debug

A data processing system and method generates debug messages by permitting an external debug tool to have real-time trace functionality. A data processor executes a plurality of data processing instructions and uses a memory for information storage. Debug circuitry generates debug messages including address translation trace messages. A memory management unit has address translation logic for implementing address translation to translate addresses between virtual and physical forms. The debug circuitry includes message generation circuitry that is coupled to the memory management unit for receiving notice when one or more address translation mappings are modified. The message generation circuitry generates an address translation trace message in response to a detection of a modification of an address translation mapping occurs and provides the address translation trace message external to the debug circuitry.

A method provides a data acquisition message of a data processing system to an external port thereof. Configuration information is written to a configuration register. It is determined if the configuration information identifies a data acquisition operation. If the data acquisition operation has been identified, data corresponding to the configuration information is written to a data register. The data in the data register and the configuration information in the configuration register are formatted into the data acquisition message. The data acquisition message is sent to the external port of the data processing system.

Data acquisition messaging using special purpose registers

A system and method time orders events that occur in various portions of the system () where different time domains () exist. Timestamping circuitry (e.g.) is provided in each of a plurality of functional circuits or modules (). The timestamping circuitry provides a message that indicates a point in time when a predetermined event occurs. An interface module () is coupled to each of the plurality of functional circuits (). The interface module () provides control information to the plurality of functional circuits () to indicate at least one operating condition that triggers the predetermined event, and to optionally specify a message format. The interface module () provides a timestamping message from one, several or all time domains at a common interface port ().

Apparatus and method for time ordering events in a system having multiple time domains

In current real-time debug systems, debug messages are transmitted through a limited bandwidth port () from an integrated circuit () to an external development system (). As some integrated circuits () become even more densely packed with multiple bus masters () and/or multiple busses () capable of generating messages, it is becoming more and more difficult for the limited bandwidth port () to sufficiently support the volume of debug messages that are to be transmitted from an integrated circuit () to an external development system (). A plurality of masks () and masking circuitry () may be used to selectively mask portions (--) of debug messages () in order to significantly improve bandwidth.

Masking within a data processing system having applicability for a development interface

A first-in, first-out (FIFO) memory system ( ) includes first and second FIFOs (A and B). First and second multiplexers ( ) each have two input terminals for receiving data. An output terminal of the first multiplexer ( ) is coupled to the first FIFO (A) and an output terminal of the second multiplexer ( ) is coupled to the second FIFO (B). In response to the data being one data type, write control logic ( ) is used to cause the data to be alternately written to the first and second FIFOs (A, B). In response to the data being a second data type, write control logic ( ) is used to cause the data to be simultaneously written to the first and second FIFOs (A, B).

First-in, first-out memory system having both simultaneous and alternating data access and method thereof

A real-time processor debug system that selectively samples address and data signals of a virtual bus of a core processor during real-time operations to reduce power consumption and to minimize performance impact due to bus loading. Gating logic for an embedded processor provides the virtual bus signals of a core processor, including address and data signals, to a debug interface of an embedded system chip or integrated circuit (IC). The gating logic receives update data and update address signals from the debug interface to control switching on corresponding debug address and data buses. The core processor provides processor status signals to the debug interface so that the debug interface determines the particular transaction being performed by the core processor. The processor status signals indicate change of flow (COF) events as well as instruction fetch or data fetch cycles.

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Austin, TX, United States of America

Richard G Collins