Altera Corporation

Other

Richard G Cliff

Srinivas T Reddy

Cameron R McClintock

Joseph Huang

Andy Louie Lee

Bruce B Pedersen

Chiakang Sung

Christopher F Lane

L Todd Cope

Bonnie I Wang

Kerry S Veenstra

Bahram Ahanin

William W Leong

David Edward Jefferson

Francis B Heile

David Wolk Mendel

Brian D Johnson

James A Watson

David Lewis

Rina Raman

Ketan H Zaveri

Manuel M Mejia

Wanli Chang

Vaughn Betz

Paul Leventis

Craig S Lytle

Khai Nguyen

Xiaobao Wang

Sergey Yuryevich Shumarayev

Cameron R Mc Clintock

Tim Tri Hoang

John E Turner

In Whan Kim

Wayne Yeung

Fung Fung Lee

Tien Duc Pham

Richard Yen-Hsiang Chang

Ninh D Ngo

Chiao Kai Hwang

Chris Lane

Andreas Papaliolios

Robert Richard Noel Bielby

Weiqi Ding

Thungoc M Tran

James G Schleicher

Richard Shaw Terrill

Robert R Bielby

Wilson Wong

Jeffrey T Watt

Irfan Rahim

Vikram Santurkar

Chris Wysocki

Hugh Sungki O

Robert N Bielby

Yow-Juang W Liu

Edward Aung

Alexander Marquardt

Robert R N Bielby

Kurosu R Altaf

Rakesh H Patel

Michael David Hutton

Tony K Ngai

Ping-Chen Liu

Anil Gupta

Kumara Tharmalingam

Richard Y Chang

Sriram Narayan

Michael Chan

Bruce B Pederson

Mao Du

Robert Blake

By Louis Leong, Legal Representative

William Leong, Deceased

Risa Altaf

Bruce B Pendersen

Vaughn Timothy Betz

Cameron Mcclintock

Brian Johnson

One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Another embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit including a first strip of PLL circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. Other embodiments and features are also disclosed.

Phase-locked loop architecture and clock distribution system

One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Each PMA module includes multiple CDR circuits, receives multiple serial data signals, and outputs data from those signals in parallel form. The programmable clock network allows the reference clock signals to be selectively shared by the PMA modules and the multiple-purpose PLLs. Another embodiment relates to a method of providing clock signals for multiple purposes in an integrated circuit. Clock signals are generated by a plurality of multiple-purpose PLLs and are selectively distributed to PMA modules arranged at a side of the integrated circuit and to logic circuitry arranged in a core section of the integrated circuit. The clock signals are used by circuitry in the PMA modules for supporting a plurality of data communications channels. Other embodiments and features are also disclosed.

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

PLD architecture for flexible placement of IP function blocks

One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.

A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.

Apparatus for improving performance of field programmable gate arrays and associated methods

An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.

Apparatus for configuring performance of field programmable gate arrays and associated methods

One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.

A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.

Apparatus and methods for adjusting performance of programmable logic devices

Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Von the range of signals passed by single-transistor passgates is reduced. In one arrangement, the V-Vlimit for signals propagated through NMOS passgates is raised by applying a higher V; in another arrangement, the Vis lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

Passgate structures for use in low-voltage applications

High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit ('PLD') includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.

Low-power transceiver architectures for programmable logic integrated circuit devices

Growing community of inventors

Los Altos, CA, United States of America

Richard G Cliff