Globalfoundries U.S. Inc.

Texas Instruments Corporation

Globalfoundries Inc.

Richard Francis Taylor, Iii

Alexander M Derrickson

Siraj Akhtar

Petteri Matti Litmanen

Judson Robert Holt

Jagar Singh

Alexander Lee Martin

Mankyu Yang

Haiting Wang

Alban Zaka

Tom Herrmann

Ignasi Cortes

Edward J Nowak

Vibhor Jain

Frank G Kuechenmeister

Nicholas A Polomoff

El Mehdi Bazizi

Tamilmani Ethirajan

Andreas Knorr

Saquib B Halim

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a silicon-on-insulator substrate including a semiconductor layer, a semiconductor substrate, and a dielectric layer between the semiconductor layer and the semiconductor substrate. The semiconductor substrate includes first and second doped regions, the first doped region has a first conductivity type, and the second doped region has a second conductivity type different from the first conductivity type. The structure further comprises first and second source/drain regions in the semiconductor layer, and a gate structure laterally between the first source/drain region and the second source/drain region. The first source/drain region overlaps with the first doped region, and the second source/drain region overlaps with the second doped region.

Field-effect transistors with heterogenous doped regions in the substrate of a silicon-on-insulator substrate

Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

Lateral heterojunction bipolar transistor with emitter and/or collector regrown from substrate and method

The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.

Asymmetric FET for FDSOI devices

Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

Crackstop with embedded passive radio frequency noise suppressor and method

A structure for a lateral bipolar junction transistor is provided. The structure comprising an emitter including a first concentration of a first dopant. A collector including a second concentration of the first dopant, the first concentration of the first dopant may be different from the second concentration of the first dopant. An intrinsic base may be laterally arranged between the emitter and the collector, and an extrinsic base region may be above the intrinsic base. An emitter extension may be arranged adjacent to the emitter, whereby the emitter extension laterally extends under a portion of the extrinsic base region. A halo region may be arranged adjacent to the emitter extension, whereby the halo region laterally extends under another portion of the extrinsic base region.

Lateral bipolar junction transistors having an emitter extension and a halo region

Embodiments of the disclosure provide a bipolar junction transistor (BJT) structure and related method. A BJT according to the disclosure may include a base over a semiconductor substrate. A collector is over the semiconductor substrate and laterally abuts a first horizontal end of the base. An emitter is over the semiconductor substrate and laterally abuts a second horizontal end of the base opposite the first horizontal end. A horizontal interface between the emitter and the base is smaller than a horizontal interface between the collector and the base.

Bipolar junction transistor (BJT) structure and related method

Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.

Lateral bipolar junction transistor and method

The present disclosure relates to semiconductor structures and, more particularly, to virtual drains for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches and methods of manufacture. The structure includes one or more active devices on a semiconductor on insulator material which is on top of a substrate; and a virtual drain region composed of a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate.

Virtual drain for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches

In described examples of a magnetically coupled structure on a substrate with an integrated circuit device, the structure includes a first coil in a differential configuration, a second coil located above the first coil in a generally stacked configuration, and a center tap connection to a winding of the second coil. The first coil includes a first differential terminal, a second differential terminal, and metal windings of the first coil. The first coil's metal windings form a continuous spiral electrical path between the first and second differential terminals. The first coil's metal windings include turns and crossing connections between the turns. The turns are fabricated in an integrated circuit metal wiring level, and the crossing connections are fabricated in at least one metal level other than the metal wiring level containing the turns. The center tap is positioned to create a balanced structure.

Baluns for RF signal conversion and impedance matching

A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary (or secondary) coil is formed by patterning a thick copper (Cu) metal layer, and a single-ended secondary (or primary) coil is formed by patterning a thick aluminum (Al) top metal bonding layer. Crossovers and/or cross-unders are formed using thin metal layers. One embodiment provides a stacked balun with a differential primary input winding defined in the copper layer, directly underneath a single-ended spiral winding defined in the aluminum layer. The spiral forms the single-ended secondary output of the balun and is rotated by 90&#xb0; to prevent metal shorting for its cross-under connections. Another embodiment provides a transformer with one differential primary (or secondary) coil defined in the copper layer and another differential secondary (or primary) coil defined in the aluminum layer and adding a center tap. The position of the tap is selected to compensate for phase differences and provide desired balance.

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Campbell, CA, United States of America

Richard Francis Taylor, Iii