International Business Machines Corporation

Other

Richard Francis Frankeny

Karl Hermann

Jerome A Frankeny

Ronald L Imken

Javad Haj-ali-Ahmadi

Ronald E Hunt

Mithkal M Smadi

Gregory E Beers

Verlon E Whitehead

Keith Allan Vanderlee

Adolph B Habich

Danny E Massey

Joseph LaTorre

Rolf Wustrau

Terry F Hayden

Janet Louise Rice

Paul A Farrar

James M Rakes

Krishnamurthy Venkatramani

Douglas E Clancy

Thai Quoc Ngo

John A Williamson

George P Olson

Charles R Linton

Lisa Elena Brown

Jacqueline A Shorter-Beauchamp

Krisnamurthy Venkatramani

The present invention discloses a combination media and media station storage unit for storing a multiplicity of media elements along with a media station for the media elements. The combination unit allows a media station to be stored and secured for protection while allowing connections for signals and allowing controls for the media station to be accessed while it is in a stored and secure position. The combination media and media station storage unit also has removable lids that may contain optional features for adding functionality to the combination media and media station storage unit. These features include but are not limited to speakers, electronics for remote broadcast of playback information, electronics for remote control of the media station, batteries, windows for observing media station status, etc. The combination unit also includes features for attaching a shoulder strap and a leg strap that enables a user to walk or jog while playing media and keeping the combination unit secure and stationary. The shoulder strap also has the audio cable for the headset integrated eliminating long headset cabling.

Combination media and media playstation storage unit

A media storage unit is made by z-folding either a joined or a continuous web of material planes forming a plurality of N overlaid material planes. The material planes have tabs extending from both non-folded sides symmetrical about a center line of each material plane. Slits are made starting on each non folded side and extending a length towards the center of each material plane. The two slits on each material plane are made at the mid-point of the material planes between the tabs allowing the tabs be separated. Opposing tabs on each side of the overlaid material planes and closest to a folded side are joined with a corresponding tab on a adjacent overlaid plane, the opposing tabs are deflected and joined in opposite directions. The joined tabs become the retaining side members of a plurality of pockets formed by the overlaid material planes. The folded sides become the bottoms of sequential pockets with openings in opposite directions. When the N overlaid material planes are folded and the tabs joined they form N&minus;1 separable and expandable pockets with opposing openings. Tabs are positioned adjacent to a slit and have a width extending out from the material planes and a length extending towards folded sides. The tabs may have a variety edge of geometries each of which, when joined, affects the nature of a pocket opening when the pocket is expanded. In general the tabs have a type of tapered width extending from the material planes with the widest edge at the slit and tapering to a narrower width towards a folded side of the material planes. Joined tapered tabs, create a pocket that opens a variable amount when expanded, the opening the widest at a slit. The length of the slits affect how much a pocket will separate from another adjacent pocket as the media storage unit is expanded to access a particular stored media.

Media storage unit with expandable and separable pockets

Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film. The film serves as the dielectric of a capacitor layer which is thereafter in succession patterned, covered by a dielectric, and has selectively deposited a metallic layer for interconnecting the capacitor and forming vias. The ends of the vias are thereafter subject to dendritic growth and joining metallurgy to provide stackable interconnection capability. A multilayer composite laminar stackable circuit board structure is created using, as appropriate, layers having metallic cores and layers having capacitively configured cores. The multilayer laminar stackable circuit board provides direct vertical connection between surface mounted electronic components and the power, signal and capacitive decoupling layers of the composite board through the dendrites and joining metallurgy of the via and plug formations.

Laminar stackable circuit board structure with capacitor

A method and circuit, for use with a parallel data bus of defined width, which provide a parallel data transmission and reception rate which is greater than the defined width of the parallel data bus. With respect to improving transmission, provided is a width-reduction circuit element, having at least two inputs through which are received a first set of parallel digital data signals and having one or more outputs through which are transmitted a second set of parallel digital data signals where the second set is both smaller than the first set and representative of the information contained within the first set. The one or more outputs interface with a parallel connector which is sufficient to form an operable connection with the parallel data bus of defined width. With respect to improving reception, provided is a width-expansion circuit element having one or more inputs through which are received a second set of parallel digital data signals and having at least two outputs through which are transmitted a first set of parallel digital data signals where the first set is both larger than the second set and representative of information encoded within the second set. The one or more inputs interface with a parallel connector sufficient to form an operable connection with the parallel data bus of defined width.

System for providing an increase in digital data transmission rate over

A cross-bar switch is implemented in a multiprocessor system which allows for bidirectional communication between a device and the cross-bar switch such that information may be transferred simultaneously between both. The cross-bar switch is not informed of the integrated circuit device's actions before a communication link is established. Rather, the bidirectional transmitter utilized herein allows the transmission of control information to the cross-bar switch while the cross-bar switch communicates to the integrated circuit device over the same transmission lines. Such bidirectional communication allows the designer of a multiprocessor communication system to minimize control lines and transmit both data and control signals over the same communication bus.

Data processing system and method for implementing a switch protocol in

A current source based multilevel bus driver and converter suitable to simultaneously insect precise magnitudes of current from multiple locations into common lines of a bus and then detect analog sums of the net current. The analog current sums so detected are decoded into digital equivalents corresponding to the respective current injection sources. In a typical application the current source drivers and converter are Located on separate integrated circuit chips. The reference node common to all the chips allows a reference generator on each chip to precisely define bias and transmitted current levels suitable to ensure precise values of injected current and to accurately differentiate between analog current levels in each line as an aspect of conversion into digital form and attribution as to origin.

Current source based multilevel bus driver and converter

A system and method for communicating information from a high speed digital device, such as a processor, to a high speed peripheral device over a bus which has a frequency capability materially lower than the clock rates of the respective sending and receiving devices. Multiple successive digital signals are latched, converted to analog format current source signals, transmitted over the bus in analog format, decoded into respective digital format signals at the receiving end of the bus, and sequentially provided to the peripheral device in the original order. Analog to digital and digital to analog conversion accuracy is maintained through the use of a linking current reference which defines at each end of the bus a reference signal suitable for mirrored replication. The current mirrors allow accurate integrated circuit device dimension controlled current generation and corresponding current level decoding.

High speed communication between high cycle rate electronic devices

An architecture for a high speed analog current to digital voltage converter particularly suited for integrated circuit applications. As preferably implemented, an analog signal of current form and an associated reference current are generated on a source integrated chip. The reference current line and one or more analog current lines transmit data between the source and a receiving integrated circuit chips. The high speed converter utilizes current mirrors to simultaneously evaluate the analog inputs and determine the digital equivalents through current comparisons using currents derived from the reference current. The architecture provides for switching of current sources in lower order bits responsive to the detection of input currents enabling higher order bits. Since switching of lower order bits by higher order bits is accomplished simultaneously, the analog current to digital voltage conversion is accomplished within one switch period while retaining the relatively high accuracy.

Current source referenced high speed analog to digitial converter

A reference generation and switched current source system suitable to convey data signals over a transmission line with minimum reflection through the use of active termination, transmission line current biasing, and the use of a shared referenced voltage derived from the characteristic impedance of the line as refined by integrated circuit transistor parameters at the transmitter and receiver. The integrated circuit chips connected by the transmission line each have a reference generator which defines a bias voltage for an active terminator, a bias current for injection into the transmission line, and a switched current source. The reference node interconnecting the transmitting and receiving devices conveys a voltage nominally twice the voltage at which the transmission line is biased and nominally twice the voltage increase introduced by the switched current source. The switched current source at the transmitting end, the bias current provided at the transmitting end, and the bias level of the active terminator at the receiving end of a transmission line are derived directly from the voltage on the reference node while compensating for the unique characteristics of the integrated circuit transistors in the respective chips.

Reference signal generation in a switched current source transmission

A multiple chip module architecture capable of forming structures having selectable aspect ratios which themselves form the basis for higher levels of integration in analogous manner. The modular architecture uses a flexible interconnect of patterned copper on polymer to successively reorient the connection plane between successive levels, permitting the selective stacking of module levels to create the desired aspect ratio of the multiple chip module. Interconnection between levels may be accomplished by solder reflow, direct dendritic bonding, or connection through a dendritic interposer.

Method for fabricating a multiple chip module using orthogonal

A bilateral media storage unit for storing and carrying CD ROMs, computer diskettes, removable disk storage devices and the like. The storage unit includes a discus shaped portable housing having a generally bowl shaped lower base component and a generally bowl shaped upper cover component which are coupled together at opposite points on their peripheries by selectively releasable hinges which pivotally couple the upper cover component to the lower base component and which release the upper cover component to pivot away from the lower base component when released. An accordion pleated extendable media receptacle is mounted within the portable housing. The accordion pleated extendable media receptacle includes a first group of extensible slots which are adapted to receive a first group of substantially planar storage media and a second group of extensible slots which are adapted to receive a second group of substantially planar storage media wherein the first group of extensible slots are extended in response to a pivoting of the upper cover component away from the lower base component in a first direction and wherein the second group of extensible slots are extended in response to a pivoting of the upper cover component away from the lower base component in a second direction.

Bilateral media storage unit

A socket for attaching a flip chip die or ball grid array devices to a printed circuit board substrate having a pattern of solder covered lands, with resources for removing the flip chip die or ball grid array device, resources for directly aligning the solder balls of the flip chip die or ball grid array device to the printed circuit board, resources for using an interposer of dendrite coated vias or pads to electrically and physically connect the solder balls of the flip chip die or ball grid array devices to the solder deposits of the printed circuit board, resources for having the interposer reconfigure the wiring for testing or replacement purposes, resources for utilizing the flexibility and resilience of the interposer to improve dendrite connections, and resources for heat sinking the flip chip die or ball grid array device by direct thermal contact. The socket applies an evenly distributed force to connect the aligned flip chip die or ball grid array device solder ball pattern to the underlying printed circuit board solder deposit pattern through dendrite penetration of the solder using an interposer situated between and aligned to each such solder pattern.

Socket for semi-permanently connecting a solder ball grid array device

A source terminated transmission line driver circuit with precise impedance matching capability and particularly suited for the output drivers of integrated circuit devices. The output transistors are operated in a current source mode using a common reference current, transistor dimension scaling, and current mirrors. The magnitude of the current provided by the output transistors is established to match the boundary conditions of the transmission line at turn-on and inherently matches the impedance characteristics upon the return of the reflected wave through conduction changes in the output transistors responsive to the transmission line voltage. The driver circuit transmits data signals over single or bus lines with minimum ringing.

Transmission line driver circuit for matching transmission line

Systems and methods for phase aligning the clocks signal transmitted from a source to multiple destination devices over individual transmission lines of differing impedance. According to the invention, each clock signal transmission line has associated therewith a matching pair of transmission lines connected to oscillate as a dummy loop. Matching programmable delay lines are connected in series with the clock signal line and the dummy loop lines, the delay lines being commonly controlled in response to a frequency comparison between the oscillation on the dummy loop and a direct subharmonic of the clock frequency. When the oscillation frequency of the dummy loop and the subharmonic of the base clock frequency match, the clock signal at the destination chip is phase aligned to the base clock signal at the clock chip, though shifted by one clock period. Clock signal phase alignment is automated for each destination chip subject to individualized control and is thereby automatically responsive to thermal or other changes at the clock chip or individual destination chips.

Growing community of inventors

Elgin, TX, United States of America

Richard Francis Frankeny