Apple Inc.

Richard F Russo

Deepankar Duggal

Conrado Blasco

Mridul Agarwal

Christopher M Tsay

Pradeep Kanapathipillai

Gideon N Levinsky

Shih-Chieh Wen

James Vash

Jeff Gonion

Yuan C Chou

Lior Zimet

Bernard Joseph Semeria

James Nolan Hardage

Tal Kuzi

Douglas C Holman

Debasish Chandra

Charles E Tucker

Jeffrey E Gonion

Gerard Richard Williams

Ian D Kountanis

David James Williamson

Gaurav Garg

John H Kelm

Kulin N Kothari

Muawya M Al-Otoom

Niket K Choudhary

Sean M Reynolds

Richard H Larson

Yanran Yang

Sandeep Kumar Gupta

Ronald P Hall

Shingo Suzuki

John H Mylius

Roy Gideon Moss

Rohit Kumar Gupta

Brett Stanley Feero

Rajat Goel

Shyam Sundar

Daniel U Becker

Haoyan Jia

Matthew R Johnson

Raghava Rao V Denduluri

Peter A Lisherness

Edvin Catovic

Pankaj Lnu

Chang Xu

Gerard R Williams Iii

James N Hardage Jr

Techniques are disclosed relating to physical register sharing. In some embodiments, a processor includes, in a register file, physical registers of a largest architected register size for a given operand type defined in an instruction set architecture (ISA). A register rename circuit of the processor is configured to assign a first physical register to an architected register of the largest architected register size. The register rename circuit is also configured to assign a first portion of a second physical register to a second ISA-defined architected register of a smaller size than the largest architected register size and a second portion of the second physical register to a third ISA-defined architected register of the smaller size. In the second assignment, the second and third architected registers of the smaller size are separate and distinct registers in the ISA.

Physical register sharing

Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.

Remote cache invalidation

Techniques are disclosed relating to performing remote invalidation of memory access permission information. In some embodiments, primary processor circuitry is configured to, based on execution of a remote permission table invalidate instruction (e.g., an ISA-defined instruction), send a remote invalidate command to secondary processor circuitry. The secondary processor circuitry includes secondary processor permission circuitry and is configured to, in response to the remote invalidate command sent by the primary processor, invalidate one or more entries in the secondary processor permission circuitry. In some embodiments, the secondary processor performs the invalidate without executing any instructions on the secondary processor circuitry.

Invalidation of permission information stored by another processor

Systems, apparatuses, and methods for efficient handling of subroutine epilogues. When an indirect control transfer instruction corresponding to a procedure return for a subroutine is identified, the return address and a signature are retrieved from one or more of a return address stack and the memory stack. An authenticator generates a signature based on at least a portion of the retrieved return address. While the signature is being generated, instruction processing speculatively continues. No instructions are permitted to commit yet. The generated signature is later compared to a copy of the signature generated earlier during the corresponding procedure call. A mismatch causes an exception.

Systems and methods for optimizing authentication branch instructions

Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.

DSB operation with excluded region

Disclosed techniques relate to re-use of speculative results from an incorrect execution path. In some embodiments, when a first control transfer instruction is mispredicted, a second control transfer instruction may have been executed on the wrong path because of the misprediction. Result storage circuitry may record information indicating a determined direction for the second control transfer instruction. Control flow tracker circuitry may store, for the first control transfer instruction, information indicating a reconvergence point. Re-use control circuitry may track registers written by instructions prior to the reconvergence point, determine, based on the tracked registers, that the second control transfer instruction does not depend on data from any instruction between the first control transfer instruction and the reconvergence point, and use the recorded determined direction for the second control transfer instruction, notwithstanding the misprediction of the first control transfer instruction.

Re-use of speculative control transfer instruction results from wrong path

An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

Scalable interrupts

A livelock resolution circuit may be used to detect and remove a livelock from a processor. The livelock resolution circuit may use a counter, whose value may be reset or incremented depending on a status of a retire pointer in a reorder buffer circuit (ROB). When the retire pointer fails to move from one operation to another over a period of time, the value in the counter may continuously increment to exceed a threshold, indicating that the period of time elapses without a successful retirement of an operation from the ROB. Thus, the livelock resolution circuit may determine that a livelock occurs. To remove the livelock, the livelock resolution circuit may involve a single-step operational mode, where the livelock resolution circuit may demand only one operation (or microoperation) to be executed at each step. As a result, the operation may be retired and the livelock may be removed.

Livelock detection and resolution using oldest operation tracking

Disclosed techniques relate to re-use of speculative results from an incorrect execution path. In some embodiments, when a control transfer instruction is mispredicted, a load instruction may have been executed on the wrong path. In disclosed embodiments, result storage circuitry records information that indicates destination registers of speculatively-executed load instructions including a first load instruction. Control flow tracker circuitry may store information indicating a reconvergence point for the control transfer instruction. Re-use control circuitry may track registers written by instructions prior to the reconvergence point, determine that the first load instruction does not depend on data from any instruction between the control transfer instruction and the reconvergence point, and use, as a result of the first load instruction, a value from a recorded destination register that was written based on speculative execution of the first load, notwithstanding the misprediction of the control transfer instruction.

Re-use of speculative load instruction results from wrong path

A system, e.g., a system on a chip (SOC), may include one or more processors. A processor may execute an instruction synchronization barrier (ISB) instruction to enforce an ordering constraint on instructions. To execute the ISB instruction, the processor may determine whether contexts of the processor required for execution of instructions older than the ISB instruction are consumed for the older instructions. Responsive to determining that the contexts are consumed for the older instructions, the processor may initiate fetching of an instruction younger than the ISB instruction, without waiting for the older instructions to retire.

Processing of synchronization barrier instructions

Systems, apparatuses, and methods for implementing a physical register last reference scheme are described. A system includes a processor with a mapper, history file, and freelist. When an entry in the mapper is updated with a new architectural register-to-physical register mapping, the processor creates a new history file entry for the given instruction that caused the update. The processor also searches the mapper to determine if the old physical register that was previously stored in the mapper entry is referenced by any other mapper entries. If there are no other mapper entries that reference this old physical register, then a last reference indicator is stored in the new history file entry. When the given instruction retires, the processor checks the last reference indicator in the history file entry to determine whether the old physical register can be returned to the freelist of available physical registers.

History file for previous register mapping storage and last reference indication

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San Jose, CA, United States of America

Richard F Russo