International Business Machines Corporation

Richard F Keil

Ram Kelkar

Stephen Dale Wyatt

Ilya I Novof

Jeffery Howard Oppold

Masayuki Hayashi

Robert J Savaglio

Kenneth Dean Short

Masa Hayashi

A process sort test circuit and methodology for determining performance characteristic of an IC chip. The circuit is located on an IC chip itself and comprises an input for receiving an input signal; a first path from the input to a first output for transmitting the input signal to the first output, the first path sensitive to variations in a manufacturing process for the IC chip; a second path from the input to a second output for transmitting the input signal to the second output, the second path being substantially less sensitive to the variations in the manufacturing process for the IC chip; and, a pulse generator device coupled to the first and second outputs for detecting a difference in arrival times of the input signal at the first and second outputs and for outputting a sort signal if the difference is of a preselected magnitude. The sort signal enables output indication of a performance characteristic of the IC chip.

On-demand process sorting method and apparatus

A two stage latch or shift register latch with very reduced propagation delay in the second stage, that may be used for LSSD type integrated circuits. The two stage register includes a first stage receiving and latching data. The first stage may also include a scan input for scanning in test data. The data is passed to a second stage which provides the received data as an output and latches the output. The preferred second stage includes a pair of cross coupled inverters, and a complementary clock stage. The complementary clock stage selectively passes the received data from the first stage to the output and, then, the second latch latches the output.

Flash output LSSD latch

An improved configuration of a capacitor formed with FET technology and a resistor and/or conductor is provided. In this configuration a capacitor is formed in which the diffusion zone of the substrate is used as one plate of the capacitor and what would normally be the gate electrode of an FET is used as the other plate of the capacitor, with the two plates being separated by a conventional thin dielectric gate oxide layer. An insulator, such as silicon dioxide overlays the gate electrode, and electrical connections to the gate electrode and diffusion zone are made through the insulator to allow the two plates of the capacitor to be connected to various devices or components as required. The top surface of this insulation layer is also used to form metal resistors. Depending on the value of required resistance, a second insulating layer may be used and a second level of metal used to connect segments of the resistors formed on the first layer of metal to form a longer resistor. This second layer of metal may also be used to form inductors. Moreover both inductors and resistors can be formed; however this may require a third layer of metal for connection purposes.

Integrated compact capacitor-resistor/inductor configuration

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Jonesville, VT, United States of America

Richard F Keil