Hewlett-packard Development Company, L.p.

Richard Eugene Hank

Dale Calvin Morris

Carol Linda Thompson

Teresa Louise Johnson

Uma Srinivasan

James R Callister

David H Gross

Le-Chun Wu

Ivan D Baev

Systems, methodologies, computer-readable media, and other embodiments associated with ordering instructions are described. One exemplary system embodiment can include an analysis logic configured to analyze executable instructions from an executable program. A re-write logic can be configured to re-order selected load instructions within the executable program based on latency times for the selected load instructions.

Systems and methods for re-ordering instructions

A method for optimizing a code section prior to performing register allocation for variables referenced in the plurality of computer instructions. The method includes performing at least one of a full prematerialization or a partial prematerialization for a variable in the plurality of computer instructions. The full prematerialization replaces the variable in every use of the variable in the plurality of computer instructions with one or more variants of the variable and replaces a definition of the variable with a nop instruction. The partial prematerialization replaces some but not all occurrences of the variable in uses of the variable in the plurality of computer instructions with one or more variants of the variable without replacing the definition of the variable with the nop instruction.

Replacing a variable in a use of the variable with a variant of the variable

A compiler configured for optimizing non-loop memory access instructions of a computer program to form architected memory instructions conforming to a base register auto-incrementing addressing mode. The compiler includes code for obtaining an intermediate stream of code containing pseudo-memory instructions from the non-loop memory access instructions. The intermediate stream of code includes at least one place holder instruction preserving a value associated with a base of a first non-loop memory access instruction even after the first non-loop memory instruction is converted to one of the pseudo-memory instructions. The compiler includes code for converting the intermediate stream of code using the intermediate stream of code and the at least one place holder instruction to obtain the architected memory instructions.

Straight-line post-increment optimization for memory access instructions

A method for eliminating a branch instruction in a control flow path of a computer program. The method includes providing a computer program having a plurality of basic blocks forming control flow paths, determining a cost of executing a branch instruction terminating a basic block in one of the control flow paths, determining a cost of combining basic blocks when merging the control flow paths, and eliminating the branch instruction from the basic block whose cost of execution is greater than the cost of combining the basic blocks in merging the control flow paths.

System and method for merging control flow paths

A method for selecting a basic block in a computer program comprising providing a computer program including an entry basic block and a plurality of basic blocks forming control flow paths, determining that immediate subsets of the control flow paths commencing with the entry basic block are essentially unbiased subsets, determining that the basic blocks in the immediate subsets of the flow control paths have essentially the same height, and selecting any one of the basic blocks in the immediate subsets of the flow control flow paths. The height may be a height selected from the group of heights consisting of resource height and dependence height. An article of manufacture including a computer-readable medium having instructions for selecting a basic block or for forming a new computer control flow path. A computer system comprising a computer program having instructions for selecting a basic block or for forming a new computer control flow path.

System and method for assigning basic blocks to computer control flow paths

A method of efficient code generation for modulo scheduled uncounted loops includes: assigning a given stage predicate to each instruction in each stage, including assigning a given stage predicate to each instruction in each speculative stage; and using the stage predicate to conditionally enable or disable the execution of an instruction during the prologue and epilogue execution.

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San Jose, CA, United States of America

Richard Eugene Hank