Seagate Technology Incorporated

International Business Machines Corporation

Richard Esten Bohn

David Erich Tetzlaff

Peng Li

Michael H Miller

Chung-Lung K Shum

Brian Robert Prasky

Kevin Arthur Gomez

Aaron Tsai

Sumanth Jannyavula Venkata

Charles William Thiesfeld

Charles E Vitu

Ka-shan Choy

Linda M Bigelow

A first input is processed via a first configuration of a neural network to produce a first output. The first configuration defines attributes of the neural network, such as connections between neural elements of the neural network. If the neural network requires a context switch to process a second input, a second configuration is applied to the neural network to change the attributes, and the second input is processed via the second configuration of the neural network to produce a second output.

Adaptive configuration of a neural network device

A compressed format is selected for storage of a matrix based on a computation to be performed using the matrix and architecture of a storage compute device to which the matrix is stored. Data of the matrix is stored on the storage compute device according to the compressed format. The computation is performed using the data via a computation unit that resides within the storage compute device.

Storage of a matrix on a storage compute device

A single device that provides computing system-level functionality with non-volatile storage controller functionality. These functionalities can share the same electronics.

Integrated circuit

A logical block address space of a storage compute device is reserved for use in executing commands from a host. First data is received at a first portion of the logical block address space, the first data causing a computation to be performed by the storage compute device. Second data is sent to the host via a second portion of the logical block address space, the second data describing a result of the computation.

Logical block addresses used for executing host commands

Commands associated with one or more logical block addresses are received via a host interface of a storage device. Based on a timing and sequence of the commands, an extent of a file that contains the logical block addresses is determined, the file being stored on the storage device. The logical block addresses are managed internally as a unitary data structure based on determining an association between the logical block addresses and the file.

Managing data within a storage device based on file system metadata

A data object is received at a storage compute device in response to a request from a host. A requirement of the data object is determined based on a computation to be performed on the data object. The requirement related to at least speed and capacity of media used to store the data object. A tier is selected from the storage compute device based on speed and capacity characteristics of the selected tier corresponding to the requirement of the data object. The data object is stored in the selected tier.

Storage compute device with tiered memory processing

A logical block address space of a storage compute device is reserved for use in executing commands from a host. The logical block address space is not mapped to a physical address space. First data is received at a first portion of the logical block address space, the first data causing a computation to be performed by the storage compute device. Second data is sent to the host via a second portion of the logical block address space, the second data describing a result of the computation.

Systems and methods are disclosed for distributed power delivery. In certain embodiments, an apparatus may comprise a device configured to control power to one or more power-consuming components via managing power usage among the one or more power-consuming components based on a priority of a task associated with the one or more power-consuming components. In certain embodiments, a device may comprise a processor configured to: receive a request to allow a component to expend an amount of power, determine if the request can be satisfied with an unallocated power budget managed by the processor, the unallocated power budget being an unallocated portion of a total power budget managed by the first processor, and allow the component to expend the amount of power when the request can be satisfied with the unallocated power budget.

Distributed power delivery

Displaying storage device status conditions using multi-color light emitting diodes (LEDs) involves monitoring values of a status condition of at least one persistent storage device. The values are mapped to two or more colors, and at least one multi-color LED displays the two or more colors in response to the respective values.

Displaying storage device status conditions using multi-color light emitting diode

A system for peer-to-peer vibration mitigation in a distributing computing system includes a secondary communication interface over which chassis management electronics (e.g., a chassis-level controller) and/or system storage nodes may initiate communications to in order to affect system changes that may decrease vibration-related performance degradation in the system.

Peer to peer vibration mitigation

Data is accessed in a multi-level hierarchical memory system. A request for data is received, including a virtual address for accessing the data. A translation buffer is queried to obtain an absolute address corresponding to the virtual address. Responsive to the translation buffer not containing an absolute address corresponding to the virtual address, the absolute address is obtained from a translation unit. A directory look-up is performed with the absolute address to determine whether a matching absolute address exists in the directory. A fetch request for the requested data is sent to a next level in the multi-level hierarchical memory system. Processing of the fetch request by the next level occurs in parallel with the directory lookup. The requested data is received in the primary cache to make the requested data available to be written to the primary cache.

System, method and processor for accessing data after a translation lookaside buffer miss

Disclosed is a method and apparatus providing a microprocessor the ability to reuse data cache content fetched during runahead execution. Said data is stored and later retrieved based upon the instruction address of an instruction which is accessing the data cache. The reuse mechanism allows the reduction of address generation interlocking scenarios with the ability to self-correct should the stored values be incorrect due to subtleties in the architected state of memory in multiprocessor systems.

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Shakopee, MN, United States of America

Richard Esten Bohn