International Business Machines Corporation

Richard Edward Serton

Yuen H Chan

Terence B Hook

John D Davis

Paul Alan Bunce

David S Wolpert

Antonio R Pelella

Leon Jacob Sigal

Matthew S Angyal

Richard Andre Wachnik

Arthur D Tuminaro

Ryan Michael Kruse

Provided are embodiments for a computer-implemented method for routing standard cells of an integrated circuit. Embodiments include obtaining a layout of a plurality of standard cells for routing, and determining existing output connections for each of the plurality of standard cells. Embodiments can also include generating a representation for the layout removing the existing output connections for each of the plurality of standard cells; and providing the representation of the layout to an autorouter. Also provided are embodiments for a system and computer program product for routing standard cells of an integrated circuit.

Selective exposure of standard cell output nets for improved routing solutions

Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.

Latch-up avoidance for sea-of-gates

A programmable clock control circuit includes a base block configured to control operation of the programmable clock control circuit and a chop block configured to control the width of an output clock signal of the programmable clock control circuit. The circuit also includes a pulse width variation block providing a pulse width variation output to the base block, the base block output being variable to provide at least three different output pulse widths. The circuit also includes a launch clock delay block coupled to delay the output of the base block and a scan clock delay block to delay the output pulse and a selector that causes either the scan clock delay block or the launch clock delay block to be active based on a value of a scan gate signal.

Programmable control clock circuit including scan mode

A compare circuit for comparing a first data word with a second data word includes a plurality of sub-circuits, each having a two-bit static compare stage and a dynamic complex logic stage; a dynamic compare node responsive to respective outputs of the sub-circuits; and an output latch that captures a comparison result in accordance with a logic state of the dynamic compare node. In an exemplary embodiment, a local clock generator provides a single controlling clock signal for clocking the output latch, precharging of the dynamic compare node, and clocking of the dynamic complex logic stage of the sub-circuits.

Single clock dynamic compare circuit

Growing community of inventors

Charlottesville, VA, United States of America

Richard Edward Serton