Maxim Integrated Products, Inc.

Texas Instruments Corporation

Richard Edward Boucher

William H Giolma

Johan Hendrik Huijsing

James E Chloupek

Michael H Haight

John D Morgan

Self configuring output stages of precision amplifiers that remain linear when operating into a load that may have a ground reference below the amplifier ground reference, that maintain full amplifier gain while approaching zero output, and that can provide a zero output even when operating into a load that may have a ground reference below the amplifier ground reference, that has a self configuring output stage operable with either a mid-rail or ground reference below amplifier ground, and which maintain a high output impedance when not selected even when the output is above the amplifier supply voltage, or when not powered, thereby allowing amplifier outputs from un-powered amplifiers or amplifiers operating at lower supply voltages to be connected in common for multiplexing to a common load.

Self configuring output stages of precision amplifiers

Auto-gain correction in a precision amplifier provides continuous calibration of the gain of the two differential input stages relative to each other and thus significantly minimizes the effects of device mismatch and temperature. Auto-gain correction together with auto-zero minimizes the effects of common mode input voltage on the amplifier and eliminates the need for trim associated with the matching of the two differential input stages. Improved gain matching enhances the accuracy of the auto-zero, which further improves the accuracy of auto-gain correction, resulting in a synergy with both operating together. The implementation of the auto-zero using an input pair of series capacitors in conjunction with a common input reference and a feedback pair of series capacitors in conjunction with a common feedback reference provides for decoupling the common mode voltage of the input differential pair or feedback differential pair. Various features may be used in sub-combinations as desired.

Auto-gain correction and common mode voltage cancellation in a precision amplifier

The present invention provides a semiconductor integrated circuit device and a communication device incorporating same. Two MOS (strong and weak) devices are connected to each control input of a transceiver. Both MOS devices are turned on while the supply voltage is ramping from 0V. The strong device remains on for a period of 10-20 microseconds. The strong MOS device pulls the input to a disabled state against external capacitance which is attempting to pull the input to an enabled state. The weak MOS device remains on while pulling the input to a disabled state. The input is pulled to an enabled state when an external source overcomes the weak MOS device. Once the control input is pulled beyond the input voltage threshold to the enabled state, the weak MOS device will be turned off permanently and the input will revert to a standard CMOS input with infinite input resistance.

Semiconductor integrated circuit and communication device for logic input-state control during and following power-up

The invention is a means for ensuring full current flow in the 'forward' direction in a MOS transistor, and substantially reducing (and/or eliminating) current flow in the 'reverse' direction. The forward voltage drop and reverse current are controllable and are determined by ratios of device size. In one embodiment, the present invention is a circuit coupled to an output stage transistor having an output voltage thereon to ensure current flow in one direction and to throttle current flow in a reverse direction. The circuit includes a first circuit coupled to the output transistor to progressively turn off the same as the output voltage reaches a first threshold voltage and approaches a rail voltage. The circuit further includes a second circuit coupled to the output transistor to turn off the same as the output voltage reaches a second threshold voltage where the second threshold voltage is greater than the rail voltage.

Reverse current throttling of a MOS transistor

A phase-locked loop circuit having a charge pump and a voltage controlled oscillator which includes a phase/frequency comparator having a single circuit for operating in phase or frequency modes and which uses the discharge signal from the oscillator flip flop to trigger resetting of the input flip flop and which uses a one-shot in the phase compare mode for high frequency operation.

Phase-frequency compare circuit for phase lock loop

A dropping resistor and a pair of differential current steering pairs coupled to the resistor with each operable to draw and cease drawing current through the resistor in response to associated corresponding input signals. An integrator is coupled through an emitter follower to one end of the resistor for integrating the current due to the difference in voltage from that voltage established when only one of the pair draws current through the resistor. Preferably the resistor is integrated on a semiconductor chip together with the remainder of the charge pump and integrator circuitry.

High frequency charge pump/integrator circuit

A voltage controlled oscillator circuit of a type having a tank circuit for generating oscillations which includes a means for establishing a fixed bias voltage with respect to ground at a bias end of said tank circuit, means for drawing current from an a.c. end of said tank so as to control the tank gain, and an AGC capacitor. A constant current source is coupled to the AGC capacitor for supplying it with a constant charging current. Means are provided for discharging the AGC capacitor at a voltage level determined by a ratio of resistors and a transistor emitter-base ratio.

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Santa Clara, CA, United States of America

Richard Edward Boucher