Standard Microsystems Corporation

Richard E Wahler

Jay D Popper

Jeffrey C Dunnihoo

J Glen Rockford

An interface that allows the host CPU and the keyboard controller in a PC to share a common BIOS ROM includes a logic circuit that receives a set of input signals and produces a set of signals that emulates a jump instruction op-code that causes the host CPU to vector to a specified address location in the system memory map normally reserved for the system ROM BIOS code, whenever both the host CPU and keyboard controller are contending for access to the BIOS ROM.

Shared bios ROM warm boot

A method and apparatus for providing power management functions in a computer or other electronic system which includes a primary power supply, a trickle power supply and a battery back-up power supply. A power management circuit includes a storage element which stores an indication of the current turn-on or turn-off condition of the primary power supply. The power management circuit also includes a group of logic gates which process signals which are supplied to the storage element under normal operating conditions to control the turn-on or turn-off condition of the primary power supply. The power management circuit senses when the trickle supply is deactivated due to a line power failure or the like, and subsequently switches the power supply inputs of the storage element and certain of the logic gates from the trickle supply to the battery back-up supply. A blocking signal is generated which prevents those signals which require the trickle supply for logic integrity from being applied to the storage element. In this manner, only signals which do not require the trickle supply for logic integrity are applied to the storage element while the trickle supply is deactivated.

Method and apparatus for power supply switching with logic integrity

A floppy disk data separator includes a phase lock loop which locks onto a clock signal that is synchronized to the data stream being read from the disk. The clock signal is derived from a sync counter which is reset each time a data bit is received from the disk. The output of the sync counter is an edge delayed by 1/4 of a bit time. The next edge of the clock occurs each 1/2 bit time after that until the next data bit is received. These clock signals are phase compared with clock signals produced in the phase lock loop to synchronize the clock to the disk data. In another aspect of the invention, the phase lock loop is operated in either a low-gain or high-gain mode.

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Lake Ronkonkoma, NY, United States of America

Richard E Wahler