Vtc Inc.

Control Data Corporation

Other

Richard E Hester

Tuan V Ngo

Jerry R Wahl

Jeffrey A Gleason

A delay circuit for differential signals has input terminals for receiving primary and complementary phases of the differential signals and output terminals upon which the primary and complementary phases of output differential signals are generated after a suitable delay. A differential comparator controls charging and discharging of first and second capacitors, one capacitor being provided for each phase for providing a seleced delay. The time difference between switching of the differential comparator and the subsequent voltage level transistion of the relative charges on the first and second capacitors determines the time delay dt. The delay circuit is compensated for power supply and temperature variation.

Differential signal delay circuit

An integrated, high speed, zero hold current and delay compensated charge pump operable at one of two different selectable pumping currents. The charge pump includes first and second supply terminals, a first input terminal for receiving digital charge-up control signals, a second input terminal for receiving digital charge-down control signals, and an output terminal. A first transistorized differential amplifier controls a first current flow of a first polarity between the first supply terminal and the output terminal as a function of the charge-up control signals. A second differential amplifier controls a second current flow between the first and second supply terminals as a function of the charge-down control signals. A pump current mirror produces a mirrored second current flow of a second polarity between the output terminal and the second supply terminal as a function of the second current flow.

Integrated, high speed, zero hold current and delay compensated charge

A bias current cancellation circuit provides current to the bases of a pair of transistors forming a differential amplifier. A transistor of matched characteristics to the differential amplifier pair is operated so that its base current replicates the base currents of the differential transistor pair. This replicated base current is inverted by a current mirror which is connected to the bases of the differential transistional pair. A second order cancellation error caused by base current differences in the current mirror is cancelled by a feedback circuit so that only the base current of the matching transistor affects the currents supplied to differential amplifier.

Differential amplifier with input bias current cancellation

Trimming of input offset voltage of a diferential amplifier is provided by a pair of resistance networks which are connected to the emitters of a pair of current mirror transistors. By adjusting the resistances of the resistance networks, the adjustment currents flowing through the current mirror transistors are selected to cancel out the input offset voltage of the differential amplifier. Each resistance network includes a plurality of resistors connected in series with a low resistance shorting link connected in parallel with each of the plurality of resistances. The input offset voltage is trimmed by selectively cutting the shorting links with a two-phase measure and trim process.

Input offset voltage trimming network and method

An amplifier output stage includes current limiting circuitry for limiting the current in the output stage if the output terminal is shorted to ground. The current sinking and the current sourcing output transistors each have a current limiting circuit which mirrors the collector current of the output transistor, produces a voltage which is a function of the mirrored collector current, and controls base current to the output transistor as a function of the voltage. The output current limiting function, therefore, is provided without sacrificing output voltage swing of the output stage.

Output stage current limit circuit

A bipolar integrated circuit amplifier with a cascode stage has an emitter follower biasing circuit which provides a bias voltage to the cascode stage. The cascode amplifier stage is stabilized by providing a stabilization capacitance across the base-collector junction of the emitter follower in the biasing circuit.

Stabilized cascode amplifier

An integrated circuit phase-locked loop includes a bipolar bandwidth switch for selectively coupling circuit elements of an external bandwidth filter network so as to control loop bandwidth. The bandwidth switch includes first and second switched terminal means which are coupled to the bandwidth filter network. A differential amplifier has a first control terminal coupled to the first switched terminal and a second control terminal coupled to the second switched terminal. The differential amplifier controls first and second currents as a function of a difference between potentials applied to the first and second switched terminals. A first current mirror couples the differential amplifier to the second switched terminal and controls current flow between a first supply terminal and the second switched terminal as a function of the first current. A second current mirror couples the differential amplifier to the second switched terminal and controls current flow between the second switched terminal and a second supply terminal as a function of the second current. Control means responsive to digital control signals control current flow through the differential amplifier, and thereby the impedance between the first and second switched terminals.

Bipolar bandwidth switch for use in a phase-locked loop

The voltage output of a differential amplifier is adjusted using an active feedback loop so that there is no direct current potential difference between the differential outputs of the differential amplifier. A potential difference at the differential output of a differential amplifier due to inherent bias or operating characteristics of the system is referred to as direct current offset voltage and the need to correct this condition may be referred to as differential output direct current offset voltage compensation. The feedback loop to accomplish this compensation consists of one or more stages of isolation and amplification driven by the output voltages of the differential amplifier and having a high input impedance to diminish loading of the amplifier outputs. A voltage peak detection system is used in order to isolate direct current voltage values from alternating current voltage values appearing at the differential amplifier output. This direct current peak detected value controls a current source which sums its output current to the current output of the differential amplifier to drive any direct current differential output to a minimum or zero value.

Active differential output direct current offset voltage compensation

A temperature compensated current source includes three successive source current paths to produce a controlled output current. Each current path has a different value of current flowing therein so that current fluctuations in one current path will tend to be isolated from the other current paths because of the difference in current flow. In the embodiment of the invention shown, a reference zener diode provides a reference voltage at the base of a first transistor to establish a first reference current as its emitter current. A second transistor uses the first current as the reference to establish a second current value which has a positive temperature coefficient. Third, fourth and fifth transistors use the second reference current to establish a third reference current value independent of the gain values of these transistors. In the embodiment of the invention described, the third reference current is used to establish a reference voltage stable with respect to variations in the power supply, transistor gain and resistivity fluctuations of the circuit but with increasing voltage as a function of temperature. This voltage variation is used in combination with a load to cancel the effect of the load variations with temperature by providing an increased source voltage as a function of temperature.

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Eden Prairie, MN, United States of America

Richard E Hester