Apple Inc.

Cray Research, Inc.

Other

Supercomputer Systems Limited Partnership

Silicon Graphics, Incorporated

Superconductor Systems Limited Partnership

Richard E Hessel

Jerome Francis Duluk, Jr

Sushma Shrikant Trivedi

Jack Benkual

Stephen L Dodgen

Jason Rupert Redgrave

Joseph P Bratt

Emerson S Fang

Hengwei Hsu

Vaughn Todd Arnold

Matthew N Papakipos

Sam Ng

Nathan D Tuck

George Cuan

Sidong Li

Shun Wai Go

Zhaoyu Gong

Abbas Rashid

George A Spix

Andrew E Phelps

Thomas Y Ho

Abraham Mammen

Bo Hong

Joseph P Grass

Tuan Anh Nguyen

Robert E Strout, Ii

Jimmie R Wilson

Lindy Fung

Douglas R Beard

Alexander A Silbey

Steve S Chen

Roger E Eckert

Brian D Vanderwarn

Albert Suan-Wei Tsay

Korbin S Van Dyke

Don A Van Dyke

Chetana Nagendra Keltcher

Nathan Daniel Tuck

Edward C Miller

Jon A Masamitsu

Diane M Wengelski

Gregory G Gaertner

Keith J Thompson

David M Cox

David A Seberger

James C Rasbold

Kelly T O'Hair

Timothy J Cramer

Anthony R Schooler

Linda J O'Gara

Ashok Chandramouli

Mark D Johnson

Stuart W Hawkinson

Giacomo G Brussino

Steven G Oslon

David M Barkai

Jeremiah D Burke

Thomas Y Yo

A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with a vector processor, and the processors collectively share access to a plurality of memory interfaces coupled to Dynamic Random Access read/write Memories (DRAMs). In typical embodiments the vector processor operates as a slave to the scalar processors, executing computationally intensive Single Instruction Multiple Data (SIMD) codes in response to commands received from the scalar processors. The vector processor implements a vector processing Instruction Set Architecture (ISA) including machine state, instruction set, exception model, and memory model.

Vector processor system

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Deferred shading graphics pipeline processor having advanced features

Vector processor

A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.

Method and apparatus for generating texture

A system and method for performing tangent space lighting in a deferred shading graphics processor (DSGP) encompasses blocks of the DSGP that preprocess data and a Phong shader that executes only after all fragments have been preprocessed. A preprocessor block receives texture maps specified in a variety of formats and converts those texture maps to a common format for use by the Phong shader. The preprocessor blocks provide the Phong shader with interpolated surface basis vectors (v , v , n), a vector Tb that represents in tangen/object space the texture/bump data from the texture maps, light data, material data, eye coordinates and other information used by the Phong shader to perform the lighting and bump mapping computations. The data from the preprocessor is provided for each fragment for which lighting effects need to be computed. The Phong shader computes the color of a fragment using the information provided by the preprocessor. The Phong shader performs all lighting computations in eye space, which requires it first to transform bump data from tangent space to eye space. In one embodiment the Phong hardware does this by multiplying a matrix M whose columns comprise eye space basis vectors (b , b , n) derived from the surface basis vectors (v , v , n) and the vector Tb of bump map data. The eye space basis vectors are derived by the DSGP preprocessor so that the multiplication (M&times;Tb) gives the perturbed surface normal N&prime; in eye space, reflecting the bump effects. The perturbed surface normal N&prime; is subsequently used in the lighting computations.

Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A a mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.

Graphics processor with pipeline state storage and retrieval

Structure, apparatus, and method for performing conservative hidden surface removal in a graphics processor. Culling is divided into two steps, a magnitude comparison content addressable memory cull operation (MCCAM Cull), and a subpixel cull operation. The MCCAM Cull discards primitives that are hidden completely by previously processed geometry. The Subpixel Cull takes the remaining primitives (which are partly or entirely visible), and determines the visible fragments. In one embodiment the method of performing hidden surface removal includes: selecting a current primitive comprising a plurality of stamps; comparing stamps to stamps from previously evaluated primitives; selecting a first stamp as a currently potentially visible stamp (CPVS) based on a relationship of depth states of samples in the first stamp with depth states of samples of previously evaluated stamps; comparing the CPVS to a second stamp; discarding the second stamp when no part of the second stamp would affect a final graphics display image based on the stamps that have been evaluated; discarding the CPVS and making the second stamp the CPVS, when the second stamp hides the CPVS; dispatching the CPVS and making the second stamp the CPVS when both the second stamp and the CPVS are at least partially visible in the final graphics display image; and dispatching the second stamp and the CPVS when the visibility of the second stamp and the CPVS depends on parameters evaluated later in the computer graphics pipeline.

Method and apparatus for culling in a graphics processor with deferred shading

Apparatus and methods for rendering 3D graphics images. The apparatus include a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a fragment-operations pipeline, coupled to the port and to the output, the pipeline including a stage for performing a fragment operation on a fragment on a per-pixel basis, as well as a stage for performing a fragment operation on the fragment on a per-sample basis. The stage for performing on a per-pixel basis is one of the following: a scissor-test stage, a stipple-test stage, an alpha-test stage or a colorest stage, and the stage for performing on a per-sample basis is one of the following: a Z-test stage, a blending stage or a dithering stage. The apparatus programmatically selects whether to perform a stencil test on a per-pixel or a per-sample basis and performs the stencil test on the selected basis. The apparatus also programmatically selects pixel samples for per-sample operations, where the sample selections differ with different instances of the same per-sample operation. The apparatus also programmatically selects a set of subdivisions of a pixel as samples for use in the per-sample fragment operation, programmatically assigns different weights to at least two samples in the set and performs the per-sample fragments operation on the fragment using the programmatically selected and differently weighted samples.

Apparatus and method for fragment operations in a 3D-graphics pipeline

Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures. Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mappings.

Graphics processor with deferred shading

An apparatus and methods for rendering 3D-graphics images preferably includes a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a geometry-operations pipeline, coupled to the port and to the output, the geometry-operations pipeline including a block for performing transformations. In one embodiment, the block for performing transformations includes a co-extensive logical and first physical stages, as well as a second physical stage including multiple logical stages. The second physical stage includes multiple logical stages that interleave their execution.

Apparatus and method for geometry operations in a 3D-graphics pipeline

The present invention provides post tile sorting setup in a tiled graphics pipeline architecture. In particular, the present invention determines a set of clipping points that identify intersections of a primitive with a tile. The mid-pipeline setup unit is adapted to compute a minimum depth value for that part of the primitive intersecting the tile. The mid-pipeline setup unit can be adapted to process primitives with x-coordinates that are screen based and y-coordinates that are tile based. Additionally, to the mid-pipeline setup unit is adapted to represent both line segments and triangles as quadrilaterals, wherein not all of a quadrilateral's vertices are required to describe a triangle.

Apparatus and method for performing setup operations in a 3-D graphics pipeline using unified primitive descriptors

System, apparatus and method for spatially sorting image data in a three-dimensional graphics pipeline

A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.

Growing community of inventors

Pleasanton, CA, United States of America

Richard E Hessel