Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Applied Materials, Inc.

Hewlett-packard Development, L.p.

Richard E Elder

Carl Philip Taussig

Josh N Hogan

Ping Mei

Marvin S Keshner

Hao Luo

Edward Robert Holland

Warren Bruce Jackson

Lihua Zhao

James A Brug

A method of fabricating a color filter array including providing substrate, forming a multilevel structure that is attached to the substrate, etching the multilevel structure to expose first wells in the multilevel structure, filling at least the first wells in the multilevel structure with the first color component, curing the first color component, etching the multilevel structure to expose second wells in the multilevel structure, filling at least the second wells in the multilevel structure with a second color component, and curing the second color component.

Method of fabricating a color filter array using a multilevel structure

An electronic apparatus is provided that includes a number of first components on a first substrate and a number of second components on a second substrate. A lamination material that includes a conducting material is placed between the first components and the second components. Any one first component can couple to a varied subset of second components.

Electronic apparatus

An aspect of the present invention is a logical arrangement of memory arrays. The logical arrangement includes a plurality of memory arrays deposed in a row-column configuration, a controller coupled to the plurality of memory arrays and at least one power line, at least one sense line and at least one address line coupled to the controller wherein a number of connections from the controller to the at least one power line, the at least one sense line and the at least one address line is minimized.

Logical arrangement of memory arrays

A defect management enabled PIRM including a data storage medium providing a plurality of cross point data storage arrays. Each array provides a plurality of memory cells. The arrays are allocated into separate super arrays, the separate super arrays virtually aligned as sets. A controller is also provided, capable of establishing the selection of a virtually aligned set of arrays and a virtually aligned set of memory cells. The controller is operable during a write operation to receive a word of data bits and detect a defective array in the selected virtually aligned set of memory arrays. The controller is further capable of directing the allocation of at least one data bit from the defective memory array to a spare memory array.

Defect management enabled PIRM and method

A data storage system that is adapted for storing image data in digital cameras comprises a temporary data storage circuit coupled, in use, to receive image data from the camera, and a permanent data storage circuit coupled, in use, to receive image data from the temporary data storage circuit. A control circuit is coupled to the temporary data storage circuit and the permanent data storage circuit to effect transfer of image data from the temporary data storage circuit to the permanent data storage circuit upon occurrence of a predetermined event. The permanent data storage circuit may be in the form of a write-once non-volatile memory module, which is replaceable in the storage system. The temporary data storage circuit can be a RAM or Flash memory that temporarily stores a image data from the camera when a picture is taken. Then, the user may review the picture before it is permanently stored upon the occurrence of the predetermined event. The predetermined event may comprise, for example, another picture being taken, removal of power (e.g. turning the camera off), or expiration of a preset time period.

Digital camera memory system

An electrical marking device is disposed on at least one layer of a data storage array having multiple layers of data storage medium. The marking device comprises at least one display layer that may be visually altered to display information, such as the nature, subject matter, and content of the data and amount of memory storage used. The display layer comprises a plurality of data storage cells, wherein the visual appearance of each of the data storage cells is varied depending on the value of the data bit. A method is also provided for electrically marking the content of an electrical data storage device having a storage array unit with multiple layers of data storage medium. Data is stored on an outermost layer of the data storage array to electrically provide a visual display indicating information about the stored data.

Apparatus and methods for marking content of memory storage devices

An optical disk and compatible optical disk drive enabling erasable (rewritable) optical disks to have the same format and capacity as read-only or (recordable) write-once optical disks. A reference clock track and optional additional prerecorded phase synchronization patters are provided to enable writing of any random sector with frequency and phase matching of a random sector to the preceding and following sectors. The reference clock track and other phase synchronization patterns eliminate the need for preambles and extra space for speed variation. In a first embodiment, a disk has multiple layers, with at least one rewritable data layer and at least one reference layer. A spiral track on a surface of the reference layer has prerecorded patterns to be used for clocking. In a variation of first embodiment, the reference layer is also used for radial tracking control, eliminated the need for predefined tracks in the rewritable data layers. The reference layer is produced using the same technology as for read-only media, and is therefore very precise, low cost, and permanent. An additional laser system may be required to read the reference layer. The rewritable data layers may be unpatterned prior to writing. Alternatively, the rewritable data layers may include embossed sector or block headers to augment clock phase precision. In a second example embodiment, a single circular permanent (non-erasable) clock track is provided on a rewritable medium. The disk is then divided into radial zones, so that within each zone, the angular velocity of the disk is constant. A clock signal from the permanent clock track is then ratioed for each radial zone.

Erasable digital video disk with reference clock track

A memory circuit includes a cross-point memory array having first and second sets of transverse electrodes with respective memory elements formed at the crossing-points of the first and second set electrodes. Each of the memory elements is formed to include, in at least one of its binary states, a diode element. The memory circuit also includes an addressing circuit coupled to the memory array. The addressing circuit has a first set of address lines with first diode connections between the first set address lines and the first set memory array electrodes, with the first diode connections coupling each memory array electrode in the first set to a respective unique subset of the first set address lines. The addressing circuit also has a second set of address lines with second diode connections between the second set address lines and the second set memory array electrodes, with the second diode connections coupling each memory array electrode in the second set to a respective unique subset of the second set address lines. The first and second diode connections form a permuted diode logic circuit whereby application of predetermined voltages to selected subsets of the first and second address lines enables unique addressing of a single memory element in the array. By sensing the current in the address lines the binary state of the addressed memory element may be determined. Also, by application of a writing voltage to the selected subsets of address lines, the binary state of a memory element can be changed by substantially and permanently changing the resistance thereof.

Addressing and sensing a cross-point diode memory array

A memory array and some addressing circuitry therefor are formed by creating circuit elements at the crossing-points of two layers of electrode conductors that are separated by a layer of a semiconductor material. The circuit elements formed at the crossing-points function as data storage devices in the memory array, and function as connections for a permuted addressing scheme for addressing the elements in the array. In order to construct the addressing circuitry, the electrode conductors are fabricated with a controlled geometry at selected crossing-points such that selected circuit elements have increased or decreased cross-sectional area. By applying a programming electrical signal to the electrodes, the electrical characteristics (e.g. resistance) of selected circuit elements can be changed according to the controlled electrode geometry.

Techniques for addressing cross-point diode memory arrays

A memory circuit includes a cross-point memory array having first and second sets of transverse electrodes with respective memory elements formed at the crossing-points of the first and second set electrodes. Each of the memory elements is formed to include, in at least one of its binary states, a diode element. The memory circuit also includes an addressing circuit coupled to the memory array. The addressing circuit has a first set of address lines with first diode connections between the first set address lines and the first set memory array electrodes, with the first diode connections coupling each memory array electrode in the first set to a respective unique subset of the first set address lines. The addressing circuit also has a second set of address lines with second diode connections between the second set address lines and the second set memory array electrodes, with the second diode connections coupling each memory array electrode in the second set to a respective unique subset of the second set address lines. The addressing circuit further includes at least one sense line with diode connections to each of the first set memory array electrodes and/or the second set memory array electrodes. A plurality of the memory circuits can be provided with the address lines coupled for parallel addressing, and the addressed memory element from each memory array is accessible for reading/writing using the respective sense line(s).

Parallel access of cross-point diode memory arrays

An electrostatic actuator having two-dimensional in-plane motion of a monolithic element suspended by flexures which is unstable in the open-loop and uses feedback control to operate. By adding a common bias voltage to each of the stator electrodes when the translator and stator are in the unstable equilibrium position, repulsion can be reduced to zero while the in-plane force remains in unstable equilibrium. Stabilizing the in-plane force at the unstable equilibrium position is achieved by shifting the electrical phase of the stator potential distribution in a direction to produce an in-plane force which opposes motion of the translators away from the equilibrium position. Linear control and pulse width modulation control permit altering the phase by less than the stator pitch. The drive electrodes of the translator and stator are used as position sensors for in-plane and out-of-plane relative displacements of the translator and stator concurrent with operation of the motor using either pulse-width modulation or linear control.

Electrostatic micromotor with large in-plane force and no out-of-plane force

An optical disk and compatible optical disk drive enabling erasable (rewritable) optical disks to have the same format and capacity as read-only or (recordable) write-once optical disks. A reference clock track and optional additional prerecorded phase synchronization patterns are provided to enable writing of any random sector with frequency and phase matching of a random sector to the preceding and following sectors. The reference clock track and other phase synchronization patterns eliminate the need for preambles and extra space for speed variation. In a first embodiment, a disk has multiple layers, with at least one rewritable data layer and at least one reference layer. A spiral track on a surface of the reference layer has prerecorded patterns to be used for clocking. In a variation of first embodiment, the reference layer is also used for radial tracking control, eliminating the need for predefined tracks in the rewritable data layers. The reference layer is produced using the same technology as for read-only media, and is therefore very precise, low cost, and permanent. An additional laser system may be required to read the reference layer. The rewritable data layers may be unpatterned prior to writing. Alternatively, the rewritable data layers may include embossed sector or block headers to augment clock phase precision. In a second example embodiment, a single circular permanent (non-erasable) clock track is provided on a rewritable medium. The disk is then divided into radial zones, so that within each zone, the angular velocity of the disk is constant. A clock signal from the permanent clock track is then ratioed for each radial zone.

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Palo Alto, CA, United States of America

Richard E Elder