Intel Corporation

Richard Dorrance

Deepak Dasalukunte

Hechen Wang

Satish Chandra Jha

Kathiravetpillai Sivanesan

Ignacio Javier Alvarez

David Israel Gonzalez Aguirre

S M Iftekharul Alam

Sridhar G Sharma

Lu Lu

Farhana Sheikh

Ranganath Krishnan

Renzhi Liu

Minyoung Park

Alexander W Min

Andrey Vladimirovich Belogolovy

Kenneth Foust

Maria Soledad Elli

Arvind Merwaday

Tolga Acikalin

Andrey Belogolovy

Sundar Krishnamurthy

David Gonzales Aguirre

Niranjan Mylarappa Gowda

Le Liang

Xue Zhang

A processor may include an interface configured to receive input data and instructions, and to provide processed data, a shared memory configured to store the received input data, an instruction memory configured to store the received instructions, a plurality of processing elements configured to perform a first set of arithmetic operations. The processor may further include a controller configured to control the plurality of processing elements and one or more accelerators based on the received instructions to obtain the processed data, by which the plurality of processing elements performs the first set of arithmetic operations and the one or more accelerators perform a second set of arithmetic operations based on the received input data stored in the shared memory.

Methods and devices for signal processing

The present disclosure relates to a device which includes a processor configured to: select, using sensor data, an error correction code from two or more error correction codes, the sensor data representing a physical state of the processor and/or the device; generate channel-coded data by channel-coding input data using the selected error correction code; and provide a representation of the channel-coded data to a transmitter for wireless data transmission.

Wireless device and methods for dynamic channel coding

A wireless communication device, including a radiofrequency frontend, configured to wirelessly receive a radiofrequency signal; perform one or more analog baseband operations on the received radiofrequency signal, according to a radio access technology; and output an analog signal representing an output of the analog baseband operations on the received radiofrequency signal; an error corrector, configured to perform an error correction operation on the analog signal; and output an error corrected signal in analog domain; and the analog-digital converter, configured to convert the error corrected signal to digital domain.

Analog forward error correction

Systems, methods, apparatuses, and computer-readable media. An analog router of a first supertile of a plurality of supertiles of a network on a chip (NoC) may receive a first analog output from a first compute-in-memory tile of a plurality of compute-in-memory tiles of the first supertile. The analog router may determine, based on a configuration of a neural network executing on the NoC, that a destination of the first analog output includes a second supertile of the plurality of supertiles. An analog-to-digital converter (ADC) of the analog router may convert the first analog output to a first digital output and transmit the first digital output to the second supertile via a communications bus of the NoC.

Hierarchical hybrid network on chip architecture for compute-in-memory probabilistic machine learning accelerator

Various embodiments provide apparatuses, systems, and methods for multibit analog representation, e.g., for in-memory computing. Embodiments may include a single-ended or differential ladder network to generate an analog value (e.g., a voltage or charge) based on a set of bits from a memory array. The ladder network may include a plurality of branches coupled to an output line, wherein individual branches include a capacitor with a first terminal coupled to the output line and a switch coupled to a second terminal of the capacitor. The switch may be controlled by a respective bit of the set of bits to selectively couple the second terminal of the capacitor to a first voltage node or a second voltage node based on a value of the respective bit. Other embodiments may be described and claimed.

Techniques for analog multibit data representation for in-memory computing

Techniques and mechanisms providing a mode of random number generation to satisfy a requirement for a consumer of random numbers. In an embodiment, a device comprises a Gaussian random number generator (GRNG) circuit, multiple uniform random number generator URNG circuits, and circuitry which is coupled between the GRNG circuit and the URNG circuits. Based on an indication of one or more required performance characteristics and/or one or more required statistical characteristics, a controller identifies a corresponding one of multiple available random number generation (RNG) modes. The controller communicates control signals to provide the mode with the circuitry. In another embodiment, the control signals configure the circuitry to select one or more of the URNG circuits for use in calculating random numbers with the GRNG circuit.

Device, method and system to selectively provide a mode of random number generation

Methods, apparatus, systems, and articles of manufacture providing an improved Bayesian neural network and methods and apparatus to operate the same are disclosed. An example apparatus includes an oscillator to generate a first clock signal; a resistive element to adjust a slope of a rising edge of a second clock signal; a voltage sampler to generate a sample based on at least one of (a) a first voltage of the first clock signal when a second voltage of the second clock signal satisfies a threshold or (b) a third voltage of the second clock signal when a fourth voltage of the first clock signal satisfies the threshold; and a charge pump to adjust a weight based on the sample, the weight to adjust data in a model.

Bayesian neural network and methods and apparatus to operate the same

Bayesian Inference based communication receiver employs Markov-Chain Monte-Carlo (MCMC) sampling for performing several of the main receiver functionalities. The channel estimator estimates the multipath channel coefficients corresponding to a signal received with fading. The symbol demodulator demodulates the received signal according to a QAM constellation, so as to generate a demodulated signal, and estimate the transmitted symbols. The decoder reliably decodes the demodulated signals to generate an output bit sequence, factoring in redundancy induced at a certain code rate. A universal sampler may be configured to use MCMC sampling for generating estimates of channel coefficients, transmitted symbols or decoder bits, for aforementioned functionalities, respectively. The samples may then be used in one or more of the receiver tasks: channel estimation, signal demodulation, and decoding, which leads to a more scalable, reusable, power/area efficient receiver.

Communication devices and methods based on markov-chain monte-carlo (MCMC) sampling

A communication device for a vehicle to communicate features about the vehicle's environment includes one or more processors configured to receive a communication from another device, wherein the communication includes a global reference coordinate system for an area covered by the other device and a number of allowed transmissions to be sent from the vehicle; transform stored data about the vehicle's environment based on the global reference coordinate system; divide the transformed stored data into a plurality of subsets of data; and select one or more subsets of data from the plurality of subsets for transmission according to the number of allowed transmissions.

Devices and methods for updating maps in autonomous driving systems in bandwidth constrained networks

According to various embodiments, a method for operating a vehicle may include determining a vehicular area having traffic conditions or characteristics different from traffic conditions of a current or previous location of the vehicle; obtaining traffic and driving information for the determined vehicular region; changing or updating one or more of driving model parameters of a safety driving model during operation of the vehicle based on the obtained traffic and driving information; and controlling the vehicle to operate in accordance with the safety driving model using the one or more changed or updated driving model parameters. A vehicle may seamlessly update operational rules and/or handover of traffic and driving information for transitioning from one region to another.

Systems, methods, and devices for driving control

Vehicle navigation control systems in autonomous driving rely on the accuracy of maps which include features about a vehicle's environment so that a vehicle may safely navigate through its surrounding area. Accordingly, this disclosure provides methods and devices which implement mechanisms for communicating features observed about a vehicle's environment for use in updating maps so as to provide vehicles with accurate and 'real-time' features of its surroundings while taking network resources, such as available frequency-time resources, into consideration.

A spintronic device includes a first ferromagnetic layer. The first ferromagnetic layer includes a first direction of magnetic polarization. Furthermore, the spintronic device includes a second ferromagnetic layer. The second ferromagnetic layer includes a second direction of magnetic polarization opposite to the first direction. Furthermore, the spintronic device includes a long spin lifetime layer. Furthermore, the spintronic device includes a first tunnel barrier layer disposed between the first ferromagnetic layer and the long spin lifetime layer. Furthermore, the spintronic device includes a second tunnel barrier layer disposed between the second ferromagnetic layer and the long spin lifetime layer.

Spintronic devices, duplexers, transceivers and telecommunication devices

A semiconductor package comprises a controlled voltage domain (CVD) and a master voltage domain (MVD). The MVD comprises an error-tolerance control (ETC) circuit. A basic execution block in the CVD generates a basic output value, based on at least two input values. A test execution block in the CVD generates a test digital root, based on digital roots of the input values. A digital root comparator in the CVD determines whether a digital root of the basic output value matches the test digital root. An error reporter in the CVD sends an error report to the ETC circuit in response to a determination that the digital roots do not match. The ETC may automatically adjust at least one power characteristic of the CVD, based on the error report. Other embodiments are described and claimed.

Error-tolerant architecture for power-efficient computing

According to the present disclosure, a communication device configured to power on a main receiver to receive data from a network includes: a low power receiver configured to receive a wake up packet, including a preamble, from the network and oversample the wake up packet; a circuit arrangement including: a correlator configured to correlate the oversampled portion of the preamble; a delay and adder configured to take an output of the correlator, delay the output of the correlator, and add the output of the correlator back onto itself to produce a delay output; a peak detector configured to detect a peak pattern in the delay output; a demodulator configured to calculate a decoding threshold value to produce a demodulated data; and a packet parser configured to check the demodulated data for a data set in order to selectively output a nonzero signal to power on the main receiver.

Growing community of inventors

Hillsboro, OR, United States of America

Richard Dorrance