Micrel, Incorporated

Richard Dolan

Martin J Alter

Robert W Rumsey

Haowei Wu

A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology.

Chip-scale package conversion technique for dies

In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over the surface of the FET, and the passivation layer is etched to expose almost the entire top surface of the bus strips. A copper seed layer is then formed over the surface of the wafer, and a mask is formed to expose only the seed layer over the bus strips. The seed layer over the bus strips is then copper or gold electroplated to deposit a very thick metal layer, which effectively merges with the underlaying metal layer, to reduce on-resistance. The plating metal does not need to be passivated due to its thickness and wide line/space. Other techniques may also be used for depositing a thick metal over the exposed bus strips.

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Pleasanton, CA, United States of America

Richard Dolan