Adeia Semiconductor Bonding Technologies Inc.

Etron Technology, Inc.

Etron Technology America, Inc.

Richard Dewitt Crisp

Belgacem Haba

Wael Zohni

Frank Lambrecht

Ilyas Mohammed

Yong Qin Chen

Giles Humpston

Ellis Chau

Masud Beroz

Philip Damberg

David Bazeley Tuckerman

Michael C Parris

Zhuowen Sun

Mark Kroot

Stuart E Wilson

Ronald Patrick Green

A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport. The physical layout of one version of the memory IC dispatches switching signal terminals adjacent to one short edge of the memory die to minimize the die area overhead for controller IC memory interface circuitry when used in a stacked die multi-chip package with said memory controller IC. The memory IC interface signal placement and signal count minimize signal length and circuitry for the memory bus signals.

Low-pincount high-bandwidth memory and memory bus

A microelectronic assembly () or system () includes at least one microelectronic package () having a microelectronic element () mounted face up above a first surface () of a substrate (), one or more columns () of contacts () extending in a first direction () along the microelectronic element front face. Columns (A,B,A,B) of terminals () exposed at a second surface () of the substrate extend in the first direction. First terminals () exposed at surface () in a central region () thereof having width () not more than three and one-half times a minimum pitch () of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.

Microelectronic package including microelectronic elements having stub minimization for wirebond assemblies without windows

A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for wirebond assemblies without windows

A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later.

Microelectronic element with bond elements to encapsulation surface

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

Flip-chip, face-up and face-down centerbond memory wirebond assemblies

A microelectronic package () can include lower and upper package faces (), lower terminals () at the lower package face, upper terminals () at the upper package face, first and second microelectronic elements () each having memory storage array function, and conductive interconnects () each electrically connecting at least one lower terminal with at least one upper terminal. The conductive interconnects () can include first conductive interconnects () configured to carry address in formation, signal assignments of a first set () of the first interconnects having (180) rotational symmetry about a theoretical rotational axis () with signal assignments of a second set () of first interconnects. The conductive interconnects () can also include second conductive interconnects () configured to carry data information, the position of each second conductive interconnect having (180) rotational symmetry about the rotational axis () with a position of a corresponding no-connect conductive interconnect ().

Reconfigurable PoP

Microelectronic package having at least two microelectronic elements that are horizontally spaced apart from each other

A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.

Stub minimization for assemblies without wirebonds to package substrate

A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane.

Stub minimization using duplicate sets of signal terminals

A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.

Microelectronic packaging without wirebonds to package substrate having terminals with signal assignments that mirror each other with respect to a central axis

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Hornitos, CA, United States of America

Richard Dewitt Crisp