Lsi Logic Corporation

Equator Technologies, Inc.

Hitachi, Ltd.

Other

Richard Deeley

Yatin Mundkur

Woobin Lee

Carlos Dangelo

Takeshi Miyazaki

Keiji Kojima

John Setel O'Donnell

Kiyokazu Nishioka

Benjamin Franklin Cutler

Toru Nojiri

Atsuo Kawaguchi

Christopher H Basoglu

Gregorio Gervasio

David Baker

Vinay Naik

Sarang Padalkar

Vijay K Nagasamy

Manoucher Vafai

An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.

Integrated multimedia system

An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the processor and the data transfer switch. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. As interface unit is coupled to the data streamer and has a plurality of I/O device driver units. A multiplexer coupled to the interface unit provides access between a selected number of I/O device driver units and external I/O devices via output pins.

A variable-length encode/decode processor includes a central processing unit and an instruction buffer and a getbits processing engine coupled to the central processing unit. Such a processor can be used to encode data as variable-length symbols or to decode variable-length symbols such as those found in an MPEG bitstream.

Processing circuit and method for variable-length coding and decoding

Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor

A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized. A matrix of milestones (goals in the design activity) is defined by degree of complexity (level of abstraction) of a design and for progressive stages (levels) of design activity (from concept through implementation). The milestones are defined using continuous refinement, and the design activity proceeds towards subsequent milestones. As milestones are achieved, previous design activity becomes unalterable. A feasibility stage is key to convergence of the process. Single level or multi-level estimators determine the direction of the process.

Method and system for creating and validating low level description of electronic design

On integrated circuit designs employing large, pre-defined circuit blocks, chip area utilization and signal routing is improved by permitting signals between circuit blocks surrounding (e.g., on opposite sides of) a large circuit block (megacell) to physically pass through the megacell. The megacell is laid out so that a 'parting line' is defined through the megacell. Circuits within the megacell are laid out so that no circuit 'straddles' the parting line. The megacell can then be split or stretched about the parting line to create a wiring channel. The wiring channel is used for routing signals from the surrounding cells (circuit blocks) through the large circuit block (megacell). Signals between the separated portions of the stretched or split megacell on opposite sides of the parting line may be routed in one metal layer, while connections of surrounding cells through the megacell may be routed in another metal layer. A maximum split or stretch distance is defined for which the megacell performance specifications (e.g., timing constraints) will be met. A plurality of surrounding cells may be interconnected by routing their signals in stacked wiring layers. The megacell may be split or stretched about two or more parting lines to create two or more wiring channels.

Separable cells having wiring channels for routing signals between

Signal area efficiency in integrated circuit designs is improved by increasing the information efficiency of signal wiring on an integrated circuit. Candidate signals are selected for combination by prioritizing signals according to length of travel, travel path, and information content. Signals with low information content and with greater distance between endpoints make poor utilization of fixed wiring and provide the best candidates for improvement. Candidate signals which travel similar (substantially parallel) paths from point to point across the integrated circuit are combined to improve chip area utilization efficiency. A variety of techniques are described for combining low-information-content signals onto a small number of wires, transmitting them over the small number of wires, and re-expanding them at their destination. Assuming that the combining/expanding circuitry occupies less space than the point-to-point wiring which would otherwise be required, there is a net reduction in chip area. One aspect of the invention is directed to using auto-routing switching techniques for combining signals. Another aspect is directed to applying these combining/expanding techniques to the integrated circuit design process.

Integrated circuit device having a switched routing network

High-speed internal interconnection technique for integrated circuits

A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications using a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized. A top-down design methodology is described, wherein a matrix of milestones (goals in the design activity) is defined by degree of complexity (level of abstraction) of a design and for progressive stages (levels) of design activity (from concept through implementation). The milestones are defined in a monotonic, unidirectional manner using continuous refinement, and the design activity proceeds towards subsequent milestones. As milestones are achieved, previous design activity becomes fixed and unalterable. A feasibility stage is key to convergence of the process. Single level or multi-level estimators (predictors) determine the direction of the process.

Method and system for creating and validating low level description of

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Richard Deeley