Marvell International Technology Ltd

Marvellworld Trade Ltd.

Avago Technologies General IP (singapore) Pte. Ltd.

Marvell International Limited

Marvell Asia Pte., Ltd.

Agilent Technologies, Inc.

Semiconductor Components Industries, LLC

Avago Technologies Imaging IP (singapore) Pte.ltd

Richard David Taylor

Mark David Montierth

Douglas G Keithley

Gary D Zimmerman

John David Marshall

Melvin D Bodily

Nikhil Balram

Vipin Namboodiri

Sanjay Saran Garg

Shilpi Sahu

Bipasha Ghosh

Gwyn Edwards

Loren Tomasi

Kaip Sridhar

Avinash Sodani

Ramacharan Sundararaman

James G Eldredge

Thomas Omega Wheless, Jr

Mark Griswold

John C Ciccone

Arash Elhami Khorasani

Thomas Ciccone

Matthew B Leslie

Elizabeth A Leonard

Edwards Gwyn

A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.

System and method to manage power to a desired power profile

In a general aspect, an integrated circuit (IC) can include a low-voltage region including a low-side driver circuit configured to control a low-side switch of a power converter. The IC can also include a high-voltage region including a floating region of a first conductivity and a high-voltage sensing device disposed in the floating region. The high-voltage sensing device can include a junction-field effect transistor (JFET), and a voltage divider. The voltage divider can include a first terminal coupled to a drain of the JFET, a second terminal coupled to a gate of the JFET, and a sense terminal, the voltage divider being configured to a provide, on the sense terminal. The IC can further include a high-side driver circuit coupled with the sense terminal. The high-side driver circuit can be configured to control a high-side switch of the power converter based on the voltage on the sense terminal.

Sensing device for high voltage applications

A method and system for printing comprises executing a formatter program on a removable Personal Computer (PC) card that controls printer controller functions of a printer. Printer formatter ready data is received from a host machine at a first interface of the removable PC card and print engine ready data is sent to the printer from a second interface of the removable PC card. A version of the formatter program is compared to a version of an updated formatter program. The updated formatter program is requested if the version of the formatter program is different than the version of the updated formatter program. The updated formatter program is downloaded from the host machine using the first interface when the second interface is coupled to the printer.

Printer formatter in a removable card

A pulse width modulation technique is disclosed for use in an image forming device such as a laser printer or a photocopier. The technique implements a pacer to synthesize the frequency of a serializer circuit by stretching (or shrinking) pixel pulse train data. The pacer stretches the pixel pulse train data in accord with increment data that is based upon information about the image forming device, such as the number of bits in the pixel pulse train data, the number of bits in print engine pulse train, the target print engine frequency, and the serializer frequency. The technique can be implemented with digital circuits that provide digital test data.

Pulse width modulator for a printing device

Embodiments of the present invention provide a multi-function device including a housing, a printing assembly disposed within the housing, the printing assembly being configured to print a document, and a copying assembly comprising a complementary metal-oxide-semiconductor (CMOS) image sensor and an illumination source disposed within the housing, the copying assembly further including a substantially flat transparent surface disposed in an optical path of the CMOS image sensor, the substantially flat transparent surface to support an object for image capture by the CMOS image sensor, wherein the illumination source is configured to provide illumination during image capture. Other embodiments may be described and/or claimed.

Multi-function device architecture

A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implemented using a few terminals of the ASIC.

Built-in-self-test using embedded memory and processor in an application specific intergrated circuit

The invention includes a system and the associated method for decoding multiple video signals. The video signals may be component video, composite video or s-video signals each having multiple portions using a multimode video decoder. A selection stage may combine the multiple video signals and select some of their video signal portions for processing. The selection stage may time-multiplex some of the video signal portions. An analog to digital conversion stage may be shared by the time-multiplexing of the video signals. A decoder stage may decode the various signal portions and provide decoded output video signals. These feature may reduce the overall cost of the system. Various clock signals may be used to operate various stages of a multimode video decoder. Some of the clock signals may run at different frequencies and others may operate at a different phase.

Shared memory multi video channel display apparatus and methods

A shared memory video processor including signal processing circuitry. The signal processing circuitry may enable a noise reducer and a de-interlacer to share access to field buffers in a memory device to store various field lines. Some of the stored field lines may also be shared within the signal processing circuitry. The sharing of some stored field lines reduces overall memory bandwidth and capacity requirements. The signal processing circuitry may be capable of performing multiple field line processing. A set of field line buffers may be provided to store field lines for multiple field segments and may provide the data to the corresponding inputs of the signal processing circuitry. To further reduce storage, some of the field line buffers may also be shared among the signal processing circuitry.

A scaler positioning module may receive a video signal selected from among a plurality of video signals. The scaler positioning module may include scaler slots for arranging the signal path of the selected video signal through at least one scaler in the scaler positioning module. The scaler slots may enable the scaler positioning module to operate in three modes. The three modes may enable the scaler positioning module to output scaled data without memory operations, scale prior to a memory write, and scale after a memory read. A blank time optimizer (BTO) may receive data from the scaler positioning module at a first clock rate and distributed memory accesses based on a bandwidth requirement determination. The BTO may access memory at a second clock rate. The second clock rate may be slower than the first which may reduce memory bandwidth and enable another video signal to access memory faster.

Embodiments of the present invention provide an integrated circuit having analog front end (AFE) circuitry to convert an analog signal to a digital signal, the analog signal being associated with an image captured by a sensor of an imaging device, illumination drive circuitry to drive an illumination source of the imaging device, and one or more transformation elements to operate on the digital signal to provide image correction of the captured image, wherein the AFE circuitry, the illumination drive circuitry, and the one or more transformation elements are integrated on a single chip. Other embodiments may be described and/or claimed.

Smart imaging device architecture

A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC.

Built-in-self-test using embedded memory and processor in an application specific integrated circuit

In a method of generating a fuser signal for a printer, a gating signal is generated using delta-sigma modulation such that an absolute value of a deficit does not exceed a threshold. The deficit corresponds to a difference between (i) a number of positive half-cycles of an alternating current (AC) signal at which the gating signal is high and (ii) a number of negative half-cycles of the AC signal at which the gating signal is high. The gating signal is used to gate the AC signal to a fuser.

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Eagle, ID, United States of America

Richard David Taylor