Advanced Micro Devices Corporation

Ati Technologies Ulc

Microsemi Storage Solutions, Inc.

Richard David Sodke

Bradford Michael Beckmann

Sergey Blagodurov

Khaled Hamidouche

Kishore Punniyamurthy

Brandon K Potter

Robert Kristian Watson

Furkan Eris

Bin Li

A device includes a plurality of processing elements (PEs). A symmetric memory is allocated in each of the plurality of PEs. The device includes a switch connected to the plurality of PEs. The switch is to: receive, from a first processing element (PE) of the plurality of PEs, a message that includes a buffer offset, compute, based on the buffer offset, a first memory address of a first buffer in a first symmetric memory of the first PE and a second memory address of a second buffer in a second symmetric memory of a second PE of the plurality of PEs, and initiate, based on the first memory address and the second memory address, a direct memory access operation to access the first buffer and the second buffer.

Low latency offloading of collectives over a switch

One or more examples relate to an on-chip protocol analyzer provided at a physical layer of a communication interface to receive information about link control process data carried by a communication system to or from a protocol control logic of the communication interface.

On-chip link analysis

Growing community of inventors

Kelowna, Canada

Richard David Sodke