Microsemi Solutions (us), Inc.

Pmc-sierra Us, Inc.

Microsemi Storage Solutions (u.s.), Inc.

Richard David Sodke

Kuan Hua Tan

Larrie Simon Carr

Gregory Arthur Tabor

Robert Kristian Watson

Kiran Hanchinal

Mansi Mehrotra

An apparatus and method for port mirroring in a plurality of Peripheral Component Interconnect express (PCIe) interfaces includes, for each PCIe interface, output transmission ports for transmitting data to a central processing unit (CPU), receiving input ports for receiving data from the CPU, port-mirror-in (PM_IN) ports, and port-mirror-out (PM_OUT) ports provided in a PHY layer instance. The PM_OUT ports of each PHY layer instance is coupled to the PM_IN ports of a next PHY layer instance such that the PHY layer instances of the plurality of PCIe interfaces are connected in a ring bus architecture for mirroring one or more ports of the output transmission ports or the receiving input ports of a first active PHY layer instance can be mirrored to output transmission ports of a second PHY layer instance.

Port mirroring for peripheral component interconnect express devices

A PCIe bus adapted for cross clock compensation of asynchronous clocks includes one or more PHY data ports provided in a PHY layer having a transmit clock (TCLK) for timing data transmitted to a peripheral device and a receive clock (RCLK) for timing data received from the peripheral device, one or more media access control (MAC) ports provided in a MAC layer having an interface clock (PCLK) for timing data transmitted to the PHY layer and data received from the PHY layer, wherein the PCLK and one or both of the TCLK and the RCLK are asynchronous, and one or more backpressure ports at an interface between the PHY layer and the MAC layer for controlling reading and writing of one of the PHY layer and the MAC layer. In some aspects, the PCLK frequency is set to be always greater than a maximum frequency of the RCLK and the TCLK.

Cross clock compensation between layers in peripheral component interconnect express

The disclosure generally relates to a PCIe switch that includes a selectively transparent bridge that selectively allows transactions to traverse between multiple PCIe domains without the encumbrance of each root complex entity requiring knowledge of the selectively transparent bridge. The bridge that enables the transactions is invisible to the root complex entity in a host and drive switch domain of the PCIe switch. No address translation of the transactions is required because the drive switch domain address map is a subset of the host switch domain address map. The bridge allows for extremely low latency transactions between host systems and storage drives because the bridge allows the storage drive to read the Direct Memory Access (DMA) Scatter-Gather List (SGL) directly from host memory. The bridge also allows I/O data reads and writes from the storage drive directly to the host memory without store and forward within a RAID controller's memory.

Method and switch for transferring transactions between switch domains

Provided is an apparatus and method for enabling interoperability between a serial attached small computer system interface (SAS) protocol with a peripheral component interconnect express (PCIe) protocol. A SAS-PCIe bridge includes a SAS component configured to communicate with a SAS device in a SAS domain and a PCIe component configured to communicate with a PCIe switch in a PCIe domain. The SAS component and the PCIe component are configured to convert data between the SAS protocol and the PCIe protocol.

Growing community of inventors

Burnaby, Canada

Richard David Sodke