International Business Machines Corporation

Richard Daniel Kimmel

Tong Li

David Wells Winston

Pravin Kamdar

Ali Sadigh

Ying Liu

Emrah Acar

Peter Feldmann

Ivan L Wemple

Ronald W Knepper

Lawrence F Wagner, Jr

Calvin John Bittner

Timothy S Lehner

Ching-Chao Huang

Barry G Craft

Rocco A Crea

Richard Levi

System analysis by receiving a model of a complex system design. The model includes at least one layer. The analysis includes performing a plurality of simulations of the performance of the layer. The number of simulations is determined according to a number of system components associated with the layer. The analysis further includes determining a worst-case result for a set of simulations from the plurality of simulations and assigning the worst-case result to an overall system simulation.

Multi-rate sampling for hierarchical system analysis

Methods, systems, and computer program products for machine learning model decision boundary enhancement are provided. Aspects include determining a decision boundary associated with a first machine learning model, wherein the first machine learning model is trained with an initial training set of features and associated classifications from a verification model, obtaining a plurality of new feature sets, analyzing, by the first machine learning model, the plurality of new feature sets to determine that a subset of feature sets have classification predictions within a threshold range of the decision boundary associated with the first machine learning model, inputting the subset of feature sets into the verification model to determine enhanced training data based on outputs of the verification model, and creating an enhanced machine learning model by further training the first machine learning model with the initial training data and the enhanced training data.

Decision boundary enhancement for learning models

Systems and methods of developing an integrated circuit implement selecting a desired yield for a circuit used in the integrated circuit. The desired yield corresponds to a desired failure probability of the circuit. The method includes determining a parameter threshold value that corresponds with the desired yield. The circuit passes if a parameter associated with the circuit is below the parameter threshold value and the desired yield indicates a percentage of instances of the circuit that pass according to the parameter threshold value. The method also includes using the parameter threshold value that corresponds with the desired yield during testing and improvement of a design of the integrated circuit, and providing the design of the integrated circuit for fabrication.

Iterative approach to determine failure threshold associated with desired circuit yield in integrated circuits

Methods, systems, can computer program products for optimizing statistical method of computing output yields are provided. Aspects include determining a target criteria of a system for statistical analysis, based on the target criteria, determining a statistical analysis algorithm for the simulation, determining a block size for a plurality of statistical samples of the system for a parallelization of the statistical analysis algorithm, generating the plurality of statistical samples of the system, simulating the plurality of statistical samples of the system to determine one or more output yields, calculating a confidence interval for each of the one or more output yields, wherein the confidence interval comprises a lower bound, comparing the lower bound to a threshold standard deviation of a probability density function, and adjusting the block size for the plurality of statistical samples based on determining that the lower bound is less than the threshold standard deviation.

Adaptive accelerated yield analysis

An on-demand table model for semiconductor device evaluation is provided. A method of providing on-demand table models for semiconductor device evaluation, includes measuring one or more measurement values of an instance of a semiconductor device. The method further includes providing, by a processor, a table model of the instance for the semiconductor device evaluation upon receiving a request for the semiconductor device evaluation. The method further includes generating a table entry in the table model for the one or more measurement values, the table entry including one or more evaluation values of an evaluation function for the instance.

On-demand table model for semiconductor device evaluation

A method and a system for validating initial conditions (ICs) generally provided by a user when simulating a VLSI circuit are described. Inconsistent ICs sets are detected and replaced by consistent subsets thereof. The method selects the resistance and source values in a Norton or Thevenin circuit used to enforce the IC, and detects when specified ICs are inconsistent while preserving critical or fragile ICs when a two DC-pass approach is used. It further correlates the set of consistent ICs thus obtained with an equivalent circuit and simultaneously provides an input for future use. This allows a user to be notified and given a measure of how bad the inconsistencies are. Detecting inconsistencies is achieved either by measuring the holding current or by measuring the voltage drift if the two DC-pass approach is used.

Method for testing the validity of initial-condition statements in circuit simulation, and correcting inconsistencies thereof

A process for obtaining accurate DC convergence in a DC phase of a circuit simulation program for models of field effect transistors (FETs) on a silicon-on-insulator (SOI) substrate. The process comprises running iterations of the DC phase of the circuit simulation program such that error criteria are satisfied, wherein the pseudo-time step changes at each iteration until it reaches a value such that a desired current value is achieved. DC convergence is also achieved by reducing the magnitude of the capacitive and/or charge elements connected to the floating body regions of the field effect transistors on the silicon-on-insulator substrate model during the DC phase to achieve a desired current value.

Method for obtaining DC convergence for SOI FET models in a circuit simulation program

A system and method for designing a structure such as a circuit. First the sensitivity of a circuit performance function (sensitivity data set - SDS) to at least one physical parameter is determined. Then, an estimated distribution of the design function calculated by using the SDS and random parameter values. Subsequently, the parameters corresponding to the estimated distribution was used to accurately calculate the tail. The tail is compared to a predetermined design objectives. If the objectives are not met, the design is modified and the calculation steps repeated until the design objectives are met.

Circuit design method and system therefor

The present invention relates to an improved method for computer-aided electrical circuit simulation which combines circuit partitioning, modified nodal formulation and conjugate-gradient solution method to efficiently analyze large electrical circuit networks. Circuit partitioning is used to create sub-circuits which isolate the passive elements of the electrical circuit. Modified nodal formulation is used to formulate matrices representative of the resultant sub-circuits. All matrices resulting from the sub-circuits containing only passive elements will be positive-definite symmetric and are efficiently solved using conjugate gradient method. Conjugate-gradient method is known to be an extremely efficient method for solving matrices of this type.

Conjugate gradient method in computer-aided circuit design

A read only memory utilizing a two-level cascoded current steering approach feeding a two-level common base isolation and sense amplifier network. The isolation network allows formation of a multi-way collector dot without deleterious effect upon the high speed current sensing operation. Single transistor cells with a common subcollector bed and common base rails as word lines make up the highly dense high speed array. The current source is provided by a current mirror circuit. The common-base, low impedance sense amplifier converts the sense current signal into a voltage swing which is then fed to the off-chip driver circuit via an emitter-follower pre-driver stage.

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Wappingers Falls, NY, United States of America

Richard Daniel Kimmel