Motorola Corporation

Richard D Sivan

James R Pfiester

James D Hayden

Frank K Baker

Bich-Yen Nguyen

Howard C Kirsch

Michael P Woo

Robert Bruce Davies

James David Burnett

Craig S Lage

Vida Ilderem

Diann M Dow

Juan Buxo

Mark D Griswold

James E Prendergast

John E Leiss

Iksung Lim

An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor material (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).

Insulated gate semiconductor device and method of manufacture

An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).

Interconnection structure for conductive layers

A process for forming isolation regions (20) having a self-aligned channel-stop (22) formed by implanting dopant atoms (24) through the isolation regions (22). An isolation mask (15) is formed over an active region (16) in a semiconductor substrate (10). The isolation mask can be constructed from a variety of materials including silicon nitride, silicon oxynitride, boron nitride, polysilicon, and germanium oxide. Thick isolation regions (20) are formed on either side of the isolation mask (15) and an ion implant process is carried out to form doped regions (22) in the substrate (10) immediately below the isolation regions (20). The isolation mask (15) prevents dopant atoms (24) from entering the active region (16) of the substrate (10).

Process for fabricating isolation regions in a semiconductor device

A semiconductor memory cell (10) includes vertically disposed MOS pass transistors (32, 34) and MOS inverters (12, 14) contained in trench structures in a semiconductor substrate (11). An MOS inverter (12) has a toroidal shared-gate electrode (48) overlying the wall surface of a first trench (36). A pass transistor (32) has a gate electrode (84) in a third trench (40). A first buried drain region (62) resides in the substrate (11) adjacent to the first trench (36), and is located a first distance from the substrate surface. A second buried drain region (64) resides in the substrate (11) adjacent to the second trench (32), and is located a second distance from the substrate surface. The inverter (12) and the pass transistor (32) are electrically coupled by the first and second buried layers (62, 64). The channel length (90) of the driver transistor (16) in the inverter (12) and the pass transistor (32) is determined by the first and second distances, respectively. Accordingly, the cell ratio of the memory cell (10) (ratio of W/L values) is also determined by the differential depth of the first and second buried drain regions (62, 64).

Semiconductor SRAM with trench transistors

In one embodiment, a semiconductor memory cell (10) having a trench (24) and access transistor (54) formed in a well region (20). The trench (24) substantially contains an inverter (60) which is electrically coupled to ground and power signals by buried layers (12, 18) in the substrate (11). The inverter (60) has a toroidal, shared-gate electrode (40) which electrically controls a driver transistor (32) in the wall (26) of the trench (24), and a thin-film load transistor (42) in the central portion of the trench (24). A portion of the toroidal, shared gate electrode extends to an adjacent well region (20') and contacts well region (20') at cell node (13'). A ground signal is provided to load transistor (42) at the bottom surface (28) of the trench (42). A supply signal is provided by a buried layer (18) which is integral with driver transistor (32).

Semiconductor memory cell having a trench structure

Method for forming an interconnection structure for conductive layers

A trench capacitor and transistor structure is formed in a semiconductor device. In one form, a transistor is fabricated within a cylindrical trench capacitor. The capacitor is formed within two displaced parallel planes in a substrate material, and has two electrodes which are separated by a dielectric material. The electrodes and dielectric are formed on a wall and a floor of the cylindrical trench. A column of epitaxial material is grown from the floor of the trench. A source region is formed by doping the top portion of the epitaxial column, and a drain region is formed by doping the floor of the trench. A gate electrode is deposited into the trench, creating a channel region along the sides of the epitaxial column. Thus, a transistor is also formed within the two displaced parallel planes in the substrate material.

Trench capacitor and transistor structure and method for making the same

A thin-film transistor in a semiconductor device is self-aligned and vertically oriented. In one form of the present invention, the semiconductor device (10) has a vertical wall trench (18) formed in a first dielectric layer (16) and having a predetermined depth. A first current electrode (26) is formed on a bottom surface of the trench while a second current electrode (28) overlies the first dielectric material, each current electrode preferably being formed of polysilicon. A channel region (30) connecting the first and second current electrodes lies along the vertical wall of the trench and has a length substantially equal to the predetermined depth. A control electrode (36) is located within the trench and is also preferably formed of polysilicon. The control electrode is electrically isolated from the first current electrode and the channel region by a second dielectric layer (32).

Method for making a self-aligned vertical thin-film transistor in a

A memory cell layout achieves a reduced cell area. In one embodiment, a six transitor (6T) SRAM cell has two vertical thin-film transistors (18 and 20) as load transistors, two transfer transistors (10 and 12), two latch transistors (14 and 16), and two storage nodes. NODE 1 and NODE 2 of the cell each have a minimum feature defined by trenches (60). Four of five interconnects associated with each node are located within the respective trench. For example in NODE 1, a drain of latch transistor (14), a gate of latch transistor (16), a drain of load transistor (18), and a current electrode of transfer transistor (10) are electrically coupled within or beneath one trench (60). A remaining interconnection of NODE 1, a gate of load transistor 20, is located within the trench associated with NODE 2. Thus, ten interconnects of the memory cell are contained within areas defined by two minimum features.

Integrated circuit memory device and structural layout thereof

In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results ina formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.

Method of fabricating MOS transistors using selective polysilicon

A structure and process for fabricating a fully self-aligned high-performance bipolar semiconductor device is disclosed. In accordance with one embodiment of the invention, a substrate is provided having a first surface. A heavily doped buried layer is formed in the substrate extending from the first surface and a lightly doped epitaxial layer overlies the first surface. An isolation region is formed in the epitaxial layer dividing the epitaxial layer into an active surface region and an isolation region. A base electrode is formed on a first portion of the active surface region having an opening which exposes a second portion of the active surface region. An emitter electrode, which is self-aligned to the base electrode, overlies a portion of the base electrode and extends through the opening in the base electrode making contact with the second portion of the active surface region. A collector plug is self-aligned to the active surface region at the edge of the base electrode and extends into the epitaxial layer making contact with the buried layer.

Method for forming a self-aligned bipolar transistor

A transistor device has a gate centered in an active region in which the gate does not extend beyond the active region. The active region has stem portion for the gate and a branch portion extending from each side of the stem portion for the formation of contacts. Raised polysilicon contacts are formed in the branch portions simultaneously with the gate being formed by selective polysilicon deposition. A source and drain are formed on sides of the gates while simultaneously doping the raised polysilicon contacts and the gate. A conformal insulator is etched to form holes to the raised contacts and the gate. These holes, even if over source and drain, do not penetrate to the source or drain because of the raised nature of the polysilicon contacts. Thus, the holes are filled with conductive material to form contacts over source and/or drain which do not contact source/drain. Thus there is no short from gate to source/drain even though the contact to gate is made over the active region. The gate, then, does not need to extend beyond the active region to provide for a metal contact thereto.

Transistor device with high density contacts

In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results in a formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.

MOS transistors using selective polysilicon deposition

A process for the fabrication of elevated source/drain IGFET devices is disclosed. In accordance with one embodiment of the process, a silicon substrate is provided which is divided into active and field regions by a field oxide. A gate oxide is formed over the active region and a thin layer of polycrystalline silicon and a thick layer of silicon nitride are deposited on the gate oxide. The polycrystalline silicon and the silicon nitride are etched to form a stacked structure, with the spacers having substantially the same height as the stacked structure, in the pattern of the gate electrode. Sidewall spacers are formed on the edges of the stacked structure and the silicon nitride is removed. Polycrystalline silicon is then deposited onto the polycrystalline silicon and the exposed portions of the source and drain regions to complete the gate electrode and to form the source and drain electrodes. The selectively deposited polycrystalline silicon extends upwardly from the source and drain regions onto the field oxide. The sidewall spacers provide physical and electrical isolation between the gate electrode and the adjacent source and drain electrodes.

Process for elevated source/drain field effect structure

A method for fabricating a self-aligned trench structure in a semiconductor device is disclosed. In accordance with one method for fabricating the trench structure, an oxidation resistant material having an opening is used as a masking layer. The edge of the opening in the masking layer is covered by a sidewall spacer which protects a portion of the substrate from attack by the etchant used to form the trench. The trench is filled with a trench fill material by selective deposition using a seeding material formed on the sidewall of the trench as a nucleation site. After the trench is filled, the sidewall spacer is removed and the underlying substrate is oxidized to form an electrical insulation region around the upper portion of the trench. The mask layer is removed and the remaining substrate is doped using the insulation region surrounding the trench as a dopant mask.

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Austin, TX, United States of America

Richard D Sivan