Intel Corporation

Nytell Software LLC

Brocade Communications Systems, Inc.

Brocade Communication Systems LLC

Sanera Systems, Inc.

Richard D Reohr, Jr

Dean Stuart Susnow

Brian M Collins

Joseph I Chamdani

Brian M Leitner

Dominic J Gasbarro

Tom E Burton

Litko Chan

Wilson Kaming Yee

Jie Ni

Joseph E Pelissier

Ni Jie

Timothy Barilovits

A field programmable object array integrated circuit has video data compression capability. The integrated circuit comprises an array of programmable objects and a video compression co-processor communicatively coupled to the array of objects. The video compression co-processor comprises a set of search engines and a subpixel engine. The subpixel engine can interpolate subpixels from integer pixels and shift the integer pixels by a predetermined number of subpixels. The search engines can perform a plurality of sum of absolute differences (SAD) computations between search window pixels and macroblock pixels to locate the best SAD value using either integer pixels and/or the interpolated subpixels.

Field programmable object array having image processing circuitry

Field programmable object array and video compression processor for video data compression

A technique for de-skewing a group of serial data signals respectively outputted from a group of data lanes includes simultaneously feeding a test signal to inputs of the group of data lanes and monitoring respective outputs thereof. A predetermined data element of the test signal outputted from each of the group of data lanes is respectively detected and respective elapsed times from the detection of the predetermined data element outputted from each of the group of data lanes to the detection that the predetermined data element has been outputted from all of the group of data lanes are measured. The group of serial data signals are then de-skewed by respectively delaying them in accordance with their respective measured elapsed times. The test signal may include the predetermined data element, a lane identifier, and a predetermined number of additional data symbols, the predetermined data element being a predetermined data character. The elapsed times may be measured by a group of lane tolerance counters, each counter initiating counting upon the detection of the predetermined data element in its data lane and each counter stopping counting upon the detection that the predetermined data element has been outputted from all of the group of data lanes. The group of serial data signals may be respectively delayed by a group of registers and the amount of delay of each data signal may be selected by a respective multiplexer connected to the group of registers, each multiplexer being controlled by its respective counter.

Multi-lane receiver de-skewing

Routing a data packet of an information unit sequence includes receiving at a switch a data packet of an information unit sequence of a block storage exchange from a storage client, where the sequence is associated with a source identifier and a target identifier identifying a target. A storage resource identifier corresponding to the target identifier is determined according to a forwarding table. A sequence identifier is associated with the source identifier, where the sequence identifier corresponds to the target. The source identifier and the sequence identifier are recorded at a context table, and the data packet is routed according to the storage resource identifier.

Processing data packets at a storage service module of a switch

Routing a data packet includes receiving at a switch a data packet from a storage client. The data packet is associated with a destination identifier identifying a virtual target, where the virtual target is accessible by the storage client. A storage resource identifier corresponding to the destination identifier is determined according to a forwarding table at the switch. The data packet is routed according to the storage resource identifier.

Performing block storage virtualization at a switch

Some embodiments of the present invention include data network comprising a host system having a host-fabric adapter; at least one remote system; a switch fabric which interconnects said host system via said host-fabric adapter to said remote system along different physical links for data communications; and at least one communication port provided in the host-fabric adapter of the host system including a set of transmit and receive buffers capable of sending and receiving data packets concurrently via respective transmitter and receiver at an end of a physical link, via the switched fabric, and a flow control mechanism utilized to prevent loss of data due to receive buffer overflow at the end of the physical link. Other embodiments are described and claims.

Link level packet flow control mechanism

Processing a data packet in a multiple protocol system area network is disclosed. A paddle card comprising a first paddle card that supports a first communication protocol or a second paddle card that supports a second communication protocol is received. The communication protocol supported by the received paddle card is identified. Data packets from the received paddle card are processed according to the identified communication protocol.

Processing data packets in a multiple protocol system area network

A technique for de-skewing a group of serial data signals respectively outputted from a group of data lanes includes simultaneously feeding a test signal to inputs of the group of data lanes and monitoring respective outputs thereof. A predetermined data element of the test signal outputted from each of the group of data lanes is respectively detected and respective elapsed times from the detection of the predetermined data element outputted from each of the group of data lanes to the detection that the predetermined data element has been outputted from all of the group of data lanes are measured. The group of serial data signals are then de-skewed by respectively delaying them in accordance with their respective measured elapsed times. The test signal may include the predetermined data element, a lane identifier, and a predetermined number of additional data symbols, the predetermined data element being a predetermined data character. The elapsed times may be measured by a group of lane tolerance counters, each counter initiating counting upon the detection of the predetermined data element in its data lane and each counter stopping counting upon the detection that the predetermined data element has been outputted from all of the group of data lanes. The group of serial data signals may be respectively delayed by a group of registers and the amount of delay of each data signal may be selected by a respective multiplexer connected to the group of registers, each multiplexer being controlled by its' respective counter.

An Elastic Buffer is provided to process data in a computer network and a write controller is provided to control memory storage operation of such an Elastic Buffer. The write controller may comprise a comparator mechanism which detects if link data from a source contains an IDLE signal; a Jabber counter mechanism which counts each cycle of a link clock in which an IDLE signal is not detected, and resets the count each time the IDLE signal is detected, and which asserts a DISABLE signal for a single link clock cycle if a count value reaches a programmed time-out value; and a logic gate which logically combines outputs from the comparator mechanism and the Jabber counter mechanism to generate a Write control signal for prohibiting a corresponding link data sequence from being stored in memory storage of the Elastic Buffer so as to prevent data overflow in the memory storage.

Jabber counter mechanism for elastic buffer operation

A system for determining whether a memory is connected to a controller in a node of a data network. In order to utilize non-volatile memory elsewhere in the system, it is possible to eliminate the EEPROM which is normally connected to the controller. In order to indicate that the EEPROM is deliberately missing, a pull-up resistor connected to a voltage source is connected to the chip select signal line which normally runs between the controller and the EEPROM. If a high signal is received, the controller knows that the EEPROM is deliberately missing and that non-volatile memory will be provided elsewhere in the system.

Controller which determines presence of memory in a node of a data network

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter comprises a host interface arranged to interface a host memory of the host system; a serial interface arranged to receive and transmit data from said switched fabric; a Micro-Engine (ME) arranged to work on multiple tasks based on a Virtual Interface (VI) to support data transfers via the switched fabric, and configured to issue a host request to said host interface for a host transaction including an address and length of host data to be fetched from the host memory, and an End-Of-Cell (EOC) indicator which indicates that a cell has been built for transmission via the serial interface, and to begin working on a different task without waiting for the corresponding host response of the host request from the host interface; a Scheduler arranged to supply a request and a request VI number to said Micro-Engine (ME) for work; and a Request Comparator arranged to check the current VI that is being worked on by the Micro-Engine (ME), and to generate an acknowledgment ACK or a negative acknowledgment NACK to the Scheduler depending upon whether the request VI number is currently being worked on by the Micro-Engine (ME).

Host-fabric adapter and method of connecting a host system to a channel-based switched fabric in a data network

A communication link is synchronized by a network interface having a transmitter in a core clock domain different from the link clock domain of the communication link. A link synchronization state machine controls the link synchronization process. The functionality of the link synchronization state machine is partitioned so that some of the functions of the link synchronization process are performed by the transmitter in the core clock domain.

Communication link synchronization method

A network interface controller connects a processing system to receive data from a network fabric through a serial link. The data on the link is clocked in a link clock domain that is different than the core clock domain of the network interface controller. A physical interface operates in the link clock domain. It has a pipeline architecture partitioned into an input register block, a decoder block and a link synchronization manager. The input register block receives the link clock and the data on the link, and transfers the data into the link clock domain. The decoder block has dual cascaded 8B/10B decoders receiving and decoding the data transferred by the input register block. The link synchronization manager manages the synchronization of the serial link according to the decoded data. An elastic buffer is connected to the output of the link synchronization manager. It is configured to output the decoded data in the core clock domain.

Growing community of inventors

Hillsboro, OR, United States of America

Richard D Reohr, Jr