Cray Research, Inc.

Silicon Graphics, Incorporated

Cray Research Systems, Inc.

Richard D Pribnow

Steven Lee Scott

Gerald A Schwoerer

Daniel L Kunkel

Peter G Logghe

Michael T Bye

Alan J Schiffleger

George W Leedom

Bricky A Stephenson

Galen C Flunker

John Theodore Kline

James G Bravatto

Thomas J Davis

A ring computer network system having a communication controller for controller the receipt and sending of packets or messages at each client computer. The interface associated with each client computer includes a send message buffer and a receive message buffer. The send message buffer has a send message buffer counter which increments upwardly in response to messages being received from the client computer for sending on the ring network. The communication controller sends messages from the send buffer until the send message buffer counter reaches the address or a value associated with the last received message. Similarly, the receive message buffer includes a receive message buffer counter which increments as each message is received to a receive message buffer counter value. The receive message buffer is emptied until the receive message buffer counter value is reached. The receive buffer can also have a foreground portion and a background portion. The send buffer can also have a background portion and a foreground portion of memory. The communication controller continually switches between the foreground and background portions of memory and redesignates each memory portion after the switch. The communications controller can also recognize priority schemes for the messages.

Message buffering for a computer-based network

A congestion control mechanism for a node of a modular computer network system. The mechanism includes registers for maintaining the number of undelivered requests and unanswered requests for the node and registers for the maximum number of such undelivered requests and unanswered requests. The mechanism regulates congestion on the network by throttling back or ratcheting up the allowed number of undelivered requests and unanswered requests based upon the level of busy and non-busy results of such requests and answers. Congestion is also alleviated by the implementation of a set of large and small send and receive buffers. These buffers are configurably partitioned among virtual I/O channels. Each request virtual I/O channel may utilitize congestion control.

Adaptive congestion control mechanism for modular computer networks

A memory reconfiguration system dynamically configures spare chips into memory during system operation by shifting data around defective chips. The shifting of data around an entire memory chip allows the system to correct bit, addressing, and control errors or faults within the chip. When the system detects an error, or otherwise initiates a memory reconfiguration, it transmits a configuration code to shift registers for a memory write driver. The shift registers, in response to the configuration code, shift write data so that the data is effectively shifted around a particular memory chip and into a spare memory chip. The system selectively transmits the configuration code to shift registers for a memory read driver. Therefore, the system independently shifts data written to the memory inputs and data read from the memory outputs.

Configurable spare memory chips

The present invention provides a vector processing computer system adapted for real-time I/O. The present invention combines a rotating priority interrupt scheme, dedicated real-time interrupt lines for each processor, and access to privileged communication/control modes of operation for processors operating in real-time to create a flexible hardware design adaptable for use in many different real-time applications.

Real time I/O operation in a vector processing computer system by

Maintenance modes of operation of a multiprocessing vector supercomputer system are disclosed. The modes allow diagnostics to run on a failed portion of the system while simultaneously allowing user tasks to run in a degraded performance mode. This is accomplished by assigning a processor or a group of processors to run diagnostics on an assigned portion of memory, while the operating system and user tasks are run in the remaining processors in the remaining portion of memory. In this manner, the diagnostics can isolate the problem without requiring complete shut down of the user task, while at the same time protecting the integrity of the operating system. The result is significantly reduced preventive maintenance down time, more efficient diagnosis of hardware failures, and a corresponding increase in user task run time.

Disabled memory sections for degraded operation of a vector supercomputer

The present invention provides an apparatus for monitoring access by a processor in a computing system to certain defined portions of memory. According to the present invention, the user specifies an address or range of address (the 'watchword') in memory to be monitored. Each processor contains hardware which monitors outgoing memory references. If the processor attempts to access the defined portion of memory, the present invention generates a signal which is sent back to the issuing processor to inform it that referenced the watchword in memory. The present invention has several applications. In particular however, the present invention can be used in conjunction with debugging software packages as an aid for debugging user software programs on multiprocessing computer systems. Specifically, the present invention can be used to pinpoint which processor in a multiprocessing computer system accessed the watchword portion of memory. For example, if a processor executed an instruction containing an error, causing improper calculation of a write destination address which resulted in data errors in memory, the present invention can pinpoint precisely which processor in the multiprocessing computer system executed the erroneous instruction, thus pinpointing the erroneous code to within a few instructions. An additional feature of the present invention is that it operates wholly independently and in parallel with the output circuitry of a processor. Thus, no additional levels of logic are introduced into the processor-to-memory path, and as a result the present invention does not adversely impact overall system performance.

Memory range monitoring apparatus for a multiprocessor computer system

An interprocessor communication system for a multiprocessor data processing system includes a common control circuit which includes a plurality of clusters where each cluster includes a plurality of semaphore registers and a plurality of information registers. Each type of register may be directly addressed by any processor. Each processor has a cluster code indicative of which, if any, of the clusters the processor may access. Each processor has a local control circuit in relatively close physical proximity and each local control circuit can communicate with the other local control circuits to determine whether one of its counterparts is requesting an operation. The local control circuit monitors and controls the issuance of the processor's instructions to the common control circuit. The local control circuit includes a plurality of local semaphore registers maintained with a copy of data in the common semaphore register cluster associated with that processor. The local control circuit further includes means for testing the status of a bit in the local semaphore register in response to a processor instruction requesting that the corresponding bit in the common control circuit be test and set, and for providing for the immediate issue of the instruction in the case where the bit is clear and the instruction may issue. The local control circuit also has the capability of generating a deadlock interrupt to accomodate the execution of a multiprocessing task by a single processor and to eliminate the possibility of a processor holding issue on a test and set instruction indefinitely.

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Chippewa Falls, WI, United States of America

Richard D Pribnow