Intel Corporation

Richard D Pashley

Bruce McCormick

Duane R Mills

Sachidanandan Sambandan

Brian L Dipert

William H Owen, Iii

Michael J Allen

Stephen Anthony Fischer

Mark D Winston

David R Gray

Charles H Lucas

Joseph D Schutz

Patrick P Gelsinger

Babak Sabi

David J Shield

Stephen F Sullivan

Stuart T Hopkins

Gregory K Crain

Steven E Wells

Robert N Hasbun

Mark E Bauer

Rodney R Rozman

Owen W Jungroth

Mamun Ur Rashid

Johnny Javanifard

Sherif R Sweha

David M Brown

Kim R Kokkonen

Sheau-Ming S Liu

David J Kaplan

Charles H Steele

Gustay Laub, Iii

George Blanchard

Glen Hawk

Gary J Gallagher

Gustav Laub, Iii

A method and apparatus for accessing and downloading information from the internet to a hand held computer system. The computer system includes a bus to which a processor, a display screen, input keys, and a flash memory are coupled. The flash memory stores an operating system for the computer system, search criteria, information corresponding to the search criteria downloaded from the internet, and display application software for displaying the information on the display screen.

Method and apparatus for accessing and downloading information from the internet

A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode the flash memory emulates synchronous DRAM.

Synchronous interface for a nonvolatile memory

An integrated circuit (IC) memory device having an interface coupled with a volatile random access memory (RAM) array and a nonvolatile flash memory array. Data to be written from an external device to the IC memory device is initially written to the volatile RAM array to provide for fast execution of a write operation, and is then written from the volatile RAM array to the nonvolatile flash memory array via the interface in a manner that is relatively transparent to external devices and the user. The interface may be configured to transfer data from the volatile RAM array to the external device if a read request matches an address tag field stored in the volatile RAM array. Data from first and second block addresses in the volatile RAM array and flash memory array may be merged in a flash merge buffer, and validity bits may be used to ensure that potentially stale data in the flash memory array is not used and that data coherency is maintained. Data may also be simultaneously written to or read from the volatile RAM array during at least a portion of the time in which data is being read from or written to the flash memory array. A check may be made to ensure that the flash merge buffer is empty before reading data from the flash memory array.

Integrated circuit memory and method for transferring data using a volatile memory to buffer data for a nonvolatile memory array

A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode, the flash memory emulates synchronous DRAM.

Asynchronous interface for a nonvolatile memory

A flash memory chip that can be switched into four different read modes is described. In the first read mode, asynchronous flash mode, the flash memory is read as a standard flash memory where the reading of the contents of a first address must be completed before a second address to be read can be specified. In the second read mode, synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock tick. Then, the contents stored at the addresses specified for the burst are output sequentially during subsequent clock ticks in the order in which the addresses were provided. Alternately, if a single address is provided to the flash chip when it is in the synchronous mode, the subsequent addresses for the burst will be generated within the flash chip and the data burst will then be provided as output from the flash chip. In the third read mode, asynchronous DRAM mode, the row and column addresses are strobed into the flash memory using strobe signals. The flash memory then converts the row and column addresses internally into a single address and provides as output the data stored at that single address. The flash memory does not need an extended precharge period or to be refreshed, but can be controlled by a standard DRAM controller. In the fourth read mode, synchronous DRAM mode, the flash memory emulates a synchronous DRAM.

Flash memory including a mode register for indicating synchronous or

Method and apparatus for accessing and downloading information from the

A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Microprocessor having single poly-silicon EPROM memory for programmably

A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to program memory cells within the array to one of at least three amounts of charge and thereby increase the amount of storage provided by the remaining functional blocks.

Method and circuitry for usage of partially functional nonvolatile memory

A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process-compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

An asynchronous nonvolatile memory includes a plurality of individual memory components. A burst read operation references consecutive addresses beginning with a first address, wherein the consecutive addresses are not located in a same memory component. A method of performing a burst read operation in the asynchronous nonvolatile memory includes the step of providing the first address as a current address to the plurality of individual components. A current page identified by m higher order bits of the current address is selected. Each of the individual memory components senses a location identified by the m higher order bits. An output of a selected individual memory component is enabled in accordance with n lower bits of the current address. A consecutive subsequent address is provided, wherein the current address becomes a preceding address and the consecutive subsequent address becomes the current address. The output of another selected individual memory component identified by the n lower order bits of the current address is enabled without generating wait states, if the current and preceding addresses identify a same page. The process of providing consecutive subsequent addresses and enabling the output of a memory component identified by the n lower order bits is repeated as long as the current and preceding addresses identify the same page.

Method and apparatus for performing burst read operations in an

An MOS process for fabricating multi-layer integrated circuits particularly suited for SOS fabrication is disclosed. Transistors are fabricated both on the substrate level and in an overlying polysilicon layer. Processing techniques for aligning source and drain regions with a buried gate are described. In one embodiment, a photoresist layer is exposed to light directed through the sapphire substrate, thereby employing the buried gate as a masking member. Laser annealing may be used to provide larger crystals of silicon in the polysilicon layer.

MOS/SOS Process

A process for forming an electrical contact region between layers of polysilicon with an integral polysilicon resistor during the fabrication of MOS integrated circuits is disclosed. The contact region which does not require critical alignments, may be formed directly over an active channel or buried (substrate) contact. A silicon nitride mask is formed at the location of the contact region on the first polysilicon layer thereby allowing a thick oxide to be grown on the remainder of the substrate. After removal of the silicon nitride mask, a second polysilicon layer is formed which contacts the first layer at the contact region and defines the resistor. A doping step is used to establish the resistance of the resistor. The process permits the fabrication, by way of example, of a static (bistable) MOS memory cell employing polysilicon loads with an area of approximately 1.5 mils.sup.2.

Process for forming a contact region between layers of polysilicon with

An integrated circuit, metal-oxide-semiconductor (MOS) static random-access memory (RAM) with a power-down mode is described. The bistable memory cells employed in the memory include low conductivity, depletion mode transistors used as loads. 'Zero' threshold voltage devices are employed on a low body-effect substrate to permit the powering-down of many circuits in the memory without affecting circuit performance. Several circuits employing these zero threshold devices are described.

Low power/high speed static ram

In a substrate, a process for forming a plurality of host regions of different conductivity types and dopant concentration levels. These various host regions include the channels of MOS field-effect devices, thereby providing devices of different voltage thresholds. Overlapping masking and doping provides numerous host regions with a minimum of masking.

Process for preparing a substrate for MOS devices of different thresholds

A process for fabricating MOS silicon gate transistors which provide high density and high speed devices. The process includes the use of a boron ion implantation step to prevent punch-through and to adjust the thresholds of enhancement mode transistors. Both enhancement mode and depletion mode transistors are simultaneously produced with the disclosed process.

Growing community of inventors

Roseville, CA, United States of America

Richard D Pashley